4.2.8 SAMA5D24/BGA256/DDR3L-SDRAM Software Settings

The SAMA5D24/BGA256/DDR3L-SDRAM set is part of a larger test board built on an 8-layer PCB. The board features a SAMA5D24/BGA256 MPU and two 1-Gbit Zentel DDR3L-SDRAM devices (part no: A3T1GF40CBF-GML). The DDR clock runs at 166 MHz.

Table 4-70. MPDDRC_MD Register Settings
FieldDescriptionSettingSetting Details
MDMemory Device4DDR3-SDRAM
DBW(1)Data Bus Width0Data bus width is 32 bits
Table 4-71. MPDDRC_CR Register Settings
FieldDescriptionSettingSetting Details
NCNumber of Column Bits110 bits to define the column number
NRNumber of Row Bits314 bits to define the row number
CASCAS Latency5DDR3 CAS Latency 3
DLLReset DLL(unchanged)Used only during power-up sequence
DIC_DSOutput Driver Impedance Control (Drive Strength)1Weak drive strength (DDR2) - RZQ/7 (34 [NOM], DDR3)
DIS_DLLDisable DLL1Disable DLL
ZQZQ Calibration(unchanged)Not available for DDR3-SDRAM
OCDOff-chip Driver(unchanged)Not available for DDR3-SDRAM
DQMSMask Data is Shared0DQM is not shared with another controller
ENRDMEnable Read Measure0DQS/DDR_DATA phase error correction is disabled
LC_LPDDR1Low-cost Low-power DDR1(unchanged)Not available for DDR3-SDRAM
NBNumber of Banks18 banks
NDQSNot DQS(unchanged)Not available for DDR3-SDRAM
DECODType of Decoding1Interleaved
UNALSupport Unaligned Access1Unaligned access is supported
Table 4-72. MPDDRC_TPR0 Register Settings
FieldDescriptionSetting(2)Setting Details
TRASActive to Precharge Delay36 ns
TRCDRow to Column Delay14 ns
TWRWrite Recovery Delay15 ns
TRCRow Cycle Delay49 ns
TRPRow Precharge Delay13 ns
TRRDActive BankA to Active BankBmax (8 ns, 4 ck)
TWTRInternal Write to Read Delaymax (8 ns, 4 ck)
TMRDLoad Mode Register Command to Activate or Refresh Command4 ck
Table 4-73. MPDDRC_TPR1 Register Settings
FieldDescriptionSetting(2)Setting Details
TRFCRow Cycle Delay110 ns
TXSNR Exit Self-refresh Delay to Non-Read Command120 ns
TXSRDExit Self-refresh Delay to Read Command0Not used in DLL Off mode
TXPExit Power-down Delay to First Commandmax (24 ns, 10 ck)
Table 4-74. MPDDRC_TPR2 Register Settings
FieldDescriptionSetting(2)Setting Details
TXARDExit Active Power-down Delay to Read Command in Mode “Fast Exit”(unchanged)Not available for DDR3-SDRAM
TXARDSExit Active Power-down Delay to Read Command in Mode “Slow Exit”(unchanged)Not available for DDR3-SDRAM
TRPARow Precharge All Delay(unchanged)Not available for DDR3-SDRAM
TRTPRead to Prechargemax (8 ns, 4 ck)-
TFAWFour Active Windows45 ns-
Table 4-75. MPDDRC_RD_DATA_PATH Register Settings
FieldDescriptionSettingSetting Details
SHIFT_SAMPLING(4)Shift Sampling Point of Data2Sampling point is shifted by two cycles
Table 4-76. MPDDRC_IO_CALIBR Register Settings
FieldDescriptionSettingSetting Details
RDIVResistor Divider, Output Driver Impedance4DDR3 serial impedance line = 55 ohms
TZQIOIO Calibration100TZQIO = (DDRCK × 600e-9) + 1
EN_CALIBEnable Calibration(unchanged)Not available for DDR3-SDRAM
Table 4-77. MPDDRC_RTR Register Settings
FieldDescriptionSettingSetting Details
COUNT(3)MPDDRC Refresh Timer Count1297Value needs to be computed
ADJ_REFAdjust Refresh Rate(unchanged)Not available for DDR3-SDRAM
REF_PBRefresh Per Bank(unchanged)Not available for DDR3-SDRAM
Note:
  1. If using one 32-bit data bus width SDRAM device or two 16-bit devices, then set the Data Bus Width to 32 bits (DBW = 0). If only one 16-bit data bus width SDRAM device is used, then set the Data Bus Width to 16 bits (DBW = 1).
  2. If timing values are given in nanoseconds, they must be converted in clock cycles and rounded up. tCYCLES = tns/tCK, where tCYCLES is the timing value in clock cycles, tns is the timing value in nanoseconds and tCK is the DDR clock period.

    Eg: If fCK = 166 MHz, then tCK = 1/fCK = 6 ns


    If tns = 35 ns, then tCYCLES = 35/6 = 6 clock cycles

  3. The value in the COUNT field needs to be computed.


    COUNT = tREFI/tCK

    For tREFI = 7.8 μs and tCK = 6 ns results in COUNT = 1300


    tREFI can also be calculated if the Refresh Window [ms] and Refresh Cycles are given (in the SDRAM data sheet).

    tREFI [μs] = (Refresh Window [ms]/Refresh Cycles)*fCK [MHz]*1000


    If Refresh Window = 64 ms, Refresh Cycles = 8192 and fCK = 166 MHz,

    then COUNT = (64/8192)*166*1000 = 1297

  4. In the case of DDR3-SDRAM devices, the field CAS must be set to 5, and the field SHIFT_SAMPLING must be set to 2. The DLL Off mode sets the CAS Read Latency (CRL) and the CAS Write Latency (CWL) to 6. The latency is automatically set by the controller.
Table 4-78. SAMA5D24/BGA256/DDR3L-SDRAM Register Settings
Register NameRegister AddressContents Value
MPDDRC_MD0xF000C0200x00000004
MPDDRC_CR0xF000C0080x00D0055D
MPDDRC_TPR00xF000C00C0x44439336
MPDDRC_TPR10xF000C0100x0A001413
MPDDRC_TPR20xF000C0140x00084000
MPDDRC_RD_DATA_PATH0xF000C05C0x00000002
MPDDRC_IO_CALIBR0xF000C0340x00876504
MPDDRC_RTR0xF000C0040x00000511