4.2.8 SAMA5D24/BGA256/DDR3L-SDRAM Software Settings
The SAMA5D24/BGA256/DDR3L-SDRAM set is part of a larger test board built on an 8-layer PCB. The board features a SAMA5D24/BGA256 MPU and two 1-Gbit Zentel DDR3L-SDRAM devices (part no: A3T1GF40CBF-GML). The DDR clock runs at 166 MHz.
| Field | Description | Setting | Setting Details |
|---|---|---|---|
| MD | Memory Device | 4 | DDR3-SDRAM |
| DBW(1) | Data Bus Width | 0 | Data bus width is 32 bits |
| Field | Description | Setting | Setting Details |
|---|---|---|---|
| NC | Number of Column Bits | 1 | 10 bits to define the column number |
| NR | Number of Row Bits | 3 | 14 bits to define the row number |
| CAS | CAS Latency | 5 | DDR3 CAS Latency 3 |
| DLL | Reset DLL | (unchanged) | Used only during power-up sequence |
| DIC_DS | Output Driver Impedance Control (Drive Strength) | 1 | Weak drive strength (DDR2) - RZQ/7 (34 [NOM], DDR3) |
| DIS_DLL | Disable DLL | 1 | Disable DLL |
| ZQ | ZQ Calibration | (unchanged) | Not available for DDR3-SDRAM |
| OCD | Off-chip Driver | (unchanged) | Not available for DDR3-SDRAM |
| DQMS | Mask Data is Shared | 0 | DQM is not shared with another controller |
| ENRDM | Enable Read Measure | 0 | DQS/DDR_DATA phase error correction is disabled |
| LC_LPDDR1 | Low-cost Low-power DDR1 | (unchanged) | Not available for DDR3-SDRAM |
| NB | Number of Banks | 1 | 8 banks |
| NDQS | Not DQS | (unchanged) | Not available for DDR3-SDRAM |
| DECOD | Type of Decoding | 1 | Interleaved |
| UNAL | Support Unaligned Access | 1 | Unaligned access is supported |
| Field | Description | Setting(2) | Setting Details |
|---|---|---|---|
| TRAS | Active to Precharge Delay | 36 ns | – |
| TRCD | Row to Column Delay | 14 ns | – |
| TWR | Write Recovery Delay | 15 ns | – |
| TRC | Row Cycle Delay | 49 ns | – |
| TRP | Row Precharge Delay | 13 ns | – |
| TRRD | Active BankA to Active BankB | max (8 ns, 4 ck) | – |
| TWTR | Internal Write to Read Delay | max (8 ns, 4 ck) | – |
| TMRD | Load Mode Register Command to Activate or Refresh Command | 4 ck | – |
| Field | Description | Setting(2) | Setting Details |
|---|---|---|---|
| TRFC | Row Cycle Delay | 110 ns | – |
| TXSNR | Exit Self-refresh Delay to Non-Read Command | 120 ns | – |
| TXSRD | Exit Self-refresh Delay to Read Command | 0 | Not used in DLL Off mode |
| TXP | Exit Power-down Delay to First Command | max (24 ns, 10 ck) | – |
| Field | Description | Setting(2) | Setting Details |
|---|---|---|---|
| TXARD | Exit Active Power-down Delay to Read Command in Mode “Fast Exit” | (unchanged) | Not available for DDR3-SDRAM |
| TXARDS | Exit Active Power-down Delay to Read Command in Mode “Slow Exit” | (unchanged) | Not available for DDR3-SDRAM |
| TRPA | Row Precharge All Delay | (unchanged) | Not available for DDR3-SDRAM |
| TRTP | Read to Precharge | max (8 ns, 4 ck) | - |
| TFAW | Four Active Windows | 45 ns | - |
| Field | Description | Setting | Setting Details |
|---|---|---|---|
| SHIFT_SAMPLING(4) | Shift Sampling Point of Data | 2 | Sampling point is shifted by two cycles |
| Field | Description | Setting | Setting Details |
|---|---|---|---|
| RDIV | Resistor Divider, Output Driver Impedance | 4 | DDR3 serial impedance line = 55 ohms |
| TZQIO | IO Calibration | 100 | TZQIO = (DDRCK × 600e-9) + 1 |
| EN_CALIB | Enable Calibration | (unchanged) | Not available for DDR3-SDRAM |
| Field | Description | Setting | Setting Details |
|---|---|---|---|
| COUNT(3) | MPDDRC Refresh Timer Count | 1297 | Value needs to be computed |
| ADJ_REF | Adjust Refresh Rate | (unchanged) | Not available for DDR3-SDRAM |
| REF_PB | Refresh Per Bank | (unchanged) | Not available for DDR3-SDRAM |
Note:
- If using one 32-bit data bus width SDRAM device or two 16-bit devices, then set the Data Bus Width to 32 bits (DBW = 0). If only one 16-bit data bus width SDRAM device is used, then set the Data Bus Width to 16 bits (DBW = 1).
- If timing values are given in
nanoseconds, they must be converted in clock cycles and rounded up.
tCYCLES = tns/tCK, where tCYCLES is
the timing value in clock cycles, tns is the timing value in nanoseconds
and tCK is the DDR clock period.
Eg: If fCK = 166 MHz, then tCK = 1/fCK = 6 ns
If tns = 35 ns, then tCYCLES = 35/6 = 6 clock cycles
- The value in the COUNT field needs to
be computed.
COUNT = tREFI/tCK
For tREFI = 7.8 μs and tCK = 6 ns results in COUNT = 1300
tREFI can also be calculated if the Refresh Window [ms] and Refresh Cycles are given (in the SDRAM data sheet).
tREFI [μs] = (Refresh Window [ms]/Refresh Cycles)*fCK [MHz]*1000
If Refresh Window = 64 ms, Refresh Cycles = 8192 and fCK = 166 MHz,
then COUNT = (64/8192)*166*1000 = 1297
- In the case of DDR3-SDRAM devices, the field CAS must be set to 5, and the field SHIFT_SAMPLING must be set to 2. The DLL Off mode sets the CAS Read Latency (CRL) and the CAS Write Latency (CWL) to 6. The latency is automatically set by the controller.
| Register Name | Register Address | Contents Value |
|---|---|---|
| MPDDRC_MD | 0xF000C020 | 0x00000004 |
| MPDDRC_CR | 0xF000C008 | 0x00D0055D |
| MPDDRC_TPR0 | 0xF000C00C | 0x44439336 |
| MPDDRC_TPR1 | 0xF000C010 | 0x0A001413 |
| MPDDRC_TPR2 | 0xF000C014 | 0x00084000 |
| MPDDRC_RD_DATA_PATH | 0xF000C05C | 0x00000002 |
| MPDDRC_IO_CALIBR | 0xF000C034 | 0x00876504 |
| MPDDRC_RTR | 0xF000C004 | 0x00000511 |