4.2.9 SAMA5D27/BGA289/LPDDR2-SDRAM Software Settings

The SAMA5D27/BGA289/LPDDR2-SDRAM set is an LPDDR2-SDRAM test board built on a 6-layer PCB. The board features a SAMA5D27/BGA289 MPU and one 2-Gbit AP Memory LPDDR2-SDRAM device (part no: AD220032D-AB). The DDR clock runs at 166 MHz.

Table 4-79. MPDDRC_MD Register Settings
FieldDescriptionSettingSetting Details
MDMemory Device7LPDDR2-SDRAM
DBW(1)Data Bus Width0Data bus width is 32 bits
Table 4-80. MPDDRC_CR Register Settings
FieldDescriptionSettingSetting Details
NCNumber of Column Bits09 bits to define the column number
NRNumber of Row Bits314 bits to define the row number
CASCAS Latency0LPDDR2 CAS Latency 3
DLLReset DLL(unchanged)Not available for LPDDR2-SDRAM
DIC_DSOutput Driver Impedance Control (Drive Strength)(unchanged)Not available for LPDDR2-SDRAM
DIS_DLLDisable DLL(unchanged)Not available for LPDDR2-SDRAM
ZQZQ Calibration(unchanged)Not available for LPDDR2-SDRAM
OCDOff-chip Driver(unchanged)Not available for LPDDR2-SDRAM
DQMSMask Data is Shared0DQM is not shared with another controller
ENRDMEnable Read Measure0DQS/DDR_DATA phase error correction is disabled
LC_LPDDR1Low-cost Low-power DDR1(unchanged)Not available for LPDDR2-SDRAM
NBNumber of Banks18 banks
NDQSNot DQS(unchanged)Not available for LPDDR2-SDRAM
DECODType of Decoding0Sequential
UNALSupport Unaligned Access1Unaligned access is supported
Table 4-81. MPDDRC_TPR0 Register Settings
FieldDescriptionSetting(2)Setting Details
TRASActive to Precharge Delay42 ns–
TRCDRow to Column Delay18 ns–
TWRWrite Recovery Delay15 ns–
TRCRow Cycle Delay60 ns–
TRPRow Precharge Delay18 ns–
TRRDActive BankA to Active BankB10 ns–
TWTRInternal Write to Read Delay10 ns–
TMRDLoad Mode Register Command to Activate or Refresh Command5 ck–
Table 4-82. MPDDRC_TPR1 Register Settings
FieldDescriptionSetting(2)Setting Details
TRFCRow Cycle Delay130 ns–
TXSNR Exit Self-refresh Delay to Non-Read Command140 ns–
TXSRDExit Self-refresh Delay to Read Command(unchanged)Not available for LPDDR2-SDRAM
TXPExit Power-down Delay to First Command8 ns–
Table 4-83. MPDDRC_TPR2 Register Settings
FieldDescriptionSetting(2)Setting Details
TXARDExit Active Power-down Delay to Read Command in Mode “Fast Exit”(unchanged)Not available for LPDDR2-SDRAM
TXARDSExit Active Power-down Delay to Read Command in Mode “Slow Exit”(unchanged)Not available for LPDDR2-SDRAM
TRPARow Precharge All Delay21 nsEquivalent to tRPAB
TRTPRead to Precharge8 ns–
TFAWFour Active Windows50 ns–
Table 4-84. MPDDRC_LPDDR23_LPR Register Settings
FieldDescriptionSettingSetting Details
BK_MASK_PASRBank Mask Bit/PASR0Refresh is enabled
SEG_MASKSegment Mask Bit0Segment is refreshed
DSDrive Strength240 ohm typical
Table 4-85. MPDDRC_RD_DATA_PATH Register Settings
FieldDescriptionSettingSetting Details
SHIFT_SAMPLINGShift Sampling Point of Data1Sampling point is shifted by one cycle
Table 4-86. MPDDRC_IO_CALIBR Register Settings
FieldDescriptionSettingSetting Details
RDIVResistor Divider, Output Driver Impedance4LPDDR2 serial impedance line = 60 ohms
TZQIOIO Calibration101TZQIO = (DDRCK × 600e-9) + 1
EN_CALIBEnable Calibration(unchanged)Not available for LPDDR2-SDRAM
Table 4-87. MPDDRC_RTR Register Settings
FieldDescriptionSettingSetting Details
COUNT(3)MPDDRC Refresh Timer Count1297Value needs to be computed
ADJ_REFAdjust Refresh Rate(unchanged)Not available for DDR3-SDRAM
REF_PBRefresh Per Bank(unchanged)Not available for DDR3-SDRAM
Note:
  1. If using one 32-bit data bus width SDRAM device or two 16-bit devices, then set the Data Bus Width to 32 bits (DBW = 0). If only one 16-bit data bus width SDRAM device is used, then set the Data Bus Width to 16 bits (DBW = 1).
  2. If timing values are given in nanoseconds, they must be converted in clock cycles and rounded up. tCYCLES = tns/tCK, where tCYCLES is the timing value in clock cycles, tns is the timing value in nanoseconds and tCK is the DDR clock period.

    Eg: If fCK = 166 MHz, then tCK = 1/fCK = 6 ns


    If tns = 35 ns, then tCYCLES = 35/6 = 6 clock cycles

  3. The value in the COUNT field needs to be computed.


    COUNT = tREFI/tCK

    For tREFI = 7.8 μs and tCK = 6 ns results in COUNT = 1300


    tREFI can also be calculated if the Refresh Window [ms] and Refresh Cycles are given (in the SDRAM data sheet).

    tREFI [μs] = (Refresh Window [ms]/Refresh Cycles)*fCK [MHz]*1000


    If Refresh Window = 64 ms, Refresh Cycles = 8192 and fCK = 166 MHz,

    then COUNT = (64/8192)*166*1000 = 1297

Table 4-88. SAMA5D24/BGA256/DDR3L-SDRAM Register Settings
Register NameRegister AddressContents Value
MPDDRC_MD0xF000C0200x00000004
MPDDRC_CR0xF000C0080x00D0055D
MPDDRC_TPR00xF000C00C0x44439336
MPDDRC_TPR10xF000C0100x0A001413
MPDDRC_TPR20xF000C0140x00084000
MPDDRC_LPDDR23_LPR0xF000C0280x02000000
MPDDRC_RD_DATA_PATH0xF000C05C0x00000001
MPDDRC_IO_CALIBR0xF000C0340x00876504
MPDDRC_RTR0xF000C0040x00000511