4.2.5 SAMA5D24/BGA256/LPDDR1-SDRAM Software Settings

The SAMA5D24/BGA256/LPDDR1-SDRAM set is part of a larger test board built on an 8-layer PCB. The board features a SAMA5D24/BGA256 MPU and two 256-Mbit ISSI LPDDR1-SDRAM devices (Part No.: IS43LR16160G-6BLI). The DDR clock runs at 166 MHz.

Table 4-41. MPDDRC_MD Register Settings
FieldDescriptionSettingSetting Details
MDMemory Device3LPDDR1-SDRAM
DBW(1)Data Bus Width0Data bus width is 32 bits
Table 4-42. MPDDRC_CR Register Settings
FieldDescriptionSettingSetting Details
NCNumber of Column Bits19 bits to define the column number
NRNumber of Row Bits213 bits to define the row number
CASCAS Latency3LPDDR1 CAS Latency 3
DLLReset DLL(unchanged)Used only during power-up sequence
DIC_DSOutput Driver Impedance Control (Drive Strength)(unchanged)Not available for LPDDR1-SDRAM
DIS_DLLDisable DLL(unchanged)Not available for LPDDR1-SDRAM
ZQZQ Calibration(unchanged)Not available for LPDDR1-SDRAM
OCDOff-chip Driver(unchanged)Not available for LPDDR1-SDRAM
DQMSMask Data is Shared0DQM is not shared with another controller
ENRDMEnable Read Measure0DQS/DDR_DATA phase error correction is disabled
LC_LPDDR1Low-cost Low-power DDR10Any LPDDR1 density except 2 banks
NBNumber of Banks04 banks
NDQSNot DQS(unchanged)Not available for LPDDR1-SDRAM
DECODType of Decoding0Sequential
UNALSupport Unaligned Access1Unaligned access is supported
Table 4-43. MPDDRC_TPR0 Register Settings
FieldDescriptionSetting(2)Setting Details
TRASActive to Precharge Delay42 ns–
TRCDRow to Column Delay18 ns–
TWRWrite Recovery Delay15 ns–
TRCRow Cycle Delay60 ns–
TRPRow Precharge Delay18 ns–
TRRDActive BankA to Active BankB12 ns–
TWTRInternal Write to Read Delay1 ck–
TMRDLoad Mode Register Command to Activate or Refresh Command2 ck–
Table 4-44. MPDDRC_TPR1 Register Settings
FieldDescriptionSetting(2)Setting Details
TRFCRow Cycle Delay70 ns–
TXSNR Exit Self-refresh Delay to Non-Read Command120 ns–
TXSRDExit Self-refresh Delay to Read Command120 ns–
TXPExit Power-down Delay to First Command1 ck–
Table 4-45. MPDDRC_TPR2 Register Settings
FieldDescriptionSetting(2)Setting Details
TXARDExit Active Power-down Delay to Read Command in Mode “Fast Exit”(unchanged)Not available for LPDDR1-SDRAM
TXARDSExit Active Power-down Delay to Read Command in Mode “Slow Exit”(unchanged)Not available for LPDDR1-SDRAM
TRPARow Precharge All Delay(unchanged)Not available for LPDDR1-SDRAM
TRTPRead to Precharge2 ck–
TFAWFour Active Windows(unchanged)Not available for LPDDR1-SDRAM
Table 4-46. MPDDRC_RD_DATA_PATH Register Settings
FieldDescriptionSettingSetting Details
SHIFT_SAMPLINGShift Sampling Point of Data1Sampling point is shifted by one cycle
Table 4-47. MPDDRC_IO_CALIBR Register Settings
FieldDescriptionSettingSetting Details
RDIVResistor Divider, Output Driver Impedance4LPDDR1 serial impedance line = 52 ohms
TZQIOIO Calibration101TZQIO = (DDRCK × 600e-9) + 1
EN_CALIBEnable Calibration1Calibration is enabled
Table 4-48. MPDDRC_RTR Register Settings
FieldDescriptionSettingSetting Details
COUNT(3)MPDDRC Refresh Timer Count1297Value needs to be computed
ADJ_REFAdjust Refresh Rate(unchanged)Not available for LPDDR1-SDRAM
REF_PBRefresh Per Bank(unchanged)Not available for LPDDR1-SDRAM
Note:
  1. If using one 32-bit data bus width SDRAM device or two 16-bit devices, set the Data Bus Width to 32 bits (DBW = 0). If only one 16-bit data bus width SDRAM device is used, set the Data Bus Width to 16 bits (DBW = 1).
  2. If timing values are given in nanoseconds, they must be converted in clock cycles and rounded up. tCYCLES = tns/tCK, where tCYCLES is the timing value in clock cycles, tns is the timing value in nanoseconds and tCK is the DDR clock period.

    Eg: If fCK = 166 MHz, then tCK = 1/fCK = 6 ns


    If tns = 35 ns, then tCYCLES = 35/6 = 6 clock cycles

  3. The value in the COUNT field needs to be computed.


    COUNT = tREFI/tCK

    For tREFI = 7.8 μs and tCK = 6 ns results in COUNT = 1300


    tREFI can also be calculated if the Refresh Window [ms] and Refresh Cycles are given (in the SDRAM data sheet).

    tREFI [μs] = (Refresh Window [ms]/Refresh Cycles)*fCK [MHz]*1000


    If Refresh Window = 64 ms, Refresh Cycles = 8192 and fCK = 166 MHz,

    then COUNT = (64/8192)*166*1000 = 1297

Table 4-49. SAMA5D24/BGA256/LPDDR1-SDRAM Register Settings
Register NameRegister AddressContents Value
MPDDRC_MD0xF000C0200x00000003
MPDDRC_CR0xF000C0080x00800539
MPDDRC_TPR00xF000C00C0x2123A337
MPDDRC_TPR10xF000C0100x0114140C
MPDDRC_TPR20xF000C0140x00082322
MPDDRC_RD_DATA_PATH0xF000C05C0x00000001
MPDDRC_IO_CALIBR0xF000C0340x00876514
MPDDRC_RTR0xF000C0040x00000511