3.3.2 SAMA5D24/BGA256/DDR2-SDRAM Devices

This set features a SAMA5D24/BGA256 MPU and two 512-Mbit ISSI DDR2-SDRAM devices (Part No.: IS43DR16320E-25DBL).

The above figure shows layer 3 of the test board focused on the DDR2-SDRAM configuration. It is used as a signal layer, contains traces for data lane 0..2 and address/control/command signals. Trace width and clearance are in accordance with the minimum required for most of these signals. There are, however, exceptions in the region underneath the MPU, where the 0.4 mm ball pitch did not allow to route traces wider than 3 mils or a larger than 3 mils clearance. In this case we must violate the 4 mils minimum width rule due to physical constraints.

Layer 5 of the test board serves as a power plane and is also used as an impedance matching reference for the neighboring signal layers (layers 4 and 6). The highlighted region shown in the above figure powers the SDRAM device. It covers a large surface and it does not feature any splits over any high-speed signal, in order to ensure a good signal integrity.

Layer 6 contains signals (see the above figure) belonging to data lane 3. All traces belonging to data lane 3 are tightly matched, with a mismatch of only 17 mils.

To calculate the trace impedance for differential signals located in inner layers, like the DQS/DQSn pair, we recommend using impedance calculators/solvers to speed up the design process. For maximum accuracy, make sure that these tools are in accordance with the IPC-2141 standard.

Using the parameters from the table Detailed Test Board Layer Stack-up, and with the trace width of 4 mils and 8 mils clearance, the trace impedance of differential pair DQS3/DQS3n is calculated to be 94.83 Ω, which is within tolerance.

In the same manner, the CK/CKn differential clock trace impedance can be calculated. The clock signal is routed on the top layer (see the figure below), has a 4 mils width, an 8 mils clearance and a 4.13 mils dielectric height, resulting in a 101.73 Ω impedance.