3.3.5 SAMA5D24/BGA256/LPDDR3-SDRAM Devices

Figure 3-31. MPUx-DRAMx LPDDR3 Device

This set features a SAMA5D24/BGA256 MPU and one 8-Gbit Micron LPDDR3-SDRAM device (Part No.: MT52L256M32D1PF-107WT).

Figure 3-32. SAMA5D24/BGA256/LPDDR3-SDRAM Layer 3

The above figure shows layer 3 of the test board focused on the LPDDR3-SDRAM configuration. It is used as a signal layer, and contains traces for data lanes 1 and 2. Trace width and clearance are in accordance with the minimum required for most of these signals. There are, however, exceptions in the region underneath the MPU, where the 0.4-mm ball pitch does not allow routing of traces wider than 3 mils. In this case, it is allowed to go below the 4 mils minimum because of high signal density.

Traces belonging in each data lane are tightly matched, with a 14-mils length mismatch for data lane 1 and a 34-mils mismatch for data lane 2. The DQS1/DQS1n and DQS2/DQS2n differential signals are also very precisely matched with a mismatch between signals from the same pair of 1 mil, respectively 3.2 mils.

Figure 3-33. SAMA5D24/BGA256/LPDDR3-SDRAM Layer 4

The above figure shows layer 4 of the test board, centered on the LPDDR3-SDRAM device. It is used as signal layer and contains both address and control/command signals. The trace width and clearance size are in accordance with the general routing rules.

The trace impedance can be calculated using the stripline impedance formula (Equation 2) or using a specialized calculator. Applying the formula results in a trace impedance Z0 = 48.17 Ω.

Figure 3-34. SAMA5D24/BGA256/LPDDR3-SDRAM Layer 1 (Top)

The above figure shows the top layer of the test board centered on the LPDDR3-SDRAM device. The differential CK/CKn signals are routed on this layer, with the commented trace width and clearance. The differential pair impedance is 101.73 Ω, very close to the 100 Ω target.

Figure 3-35. SAMA5D24/BGA256/LPDDR3-SDRAM Layer 6

The above figure shows layer 6, where data lanes 0 and 3 from the LPDDR3-SDRAM are routed.

The target impedance for DQS0/DQS0n and DQS3/DQS3n differential pairs is 100 Ω. Using an impedance calculator resulted in a value of 98.16 Ω. All power layers provide an unslotted reference plane to maintain a good signal integrity.