3.3.3 SAMA5D24/BGA256/LPDDR1-SDRAM Devices

Figure 3-23. MPUx-DRAMx LPDDR1 Device

This set features a SAMA5D24/BGA256 MPU and two 256-Mbit ISSI LPDDR1-SDRAM devices (Part No.: IS43LR16160G-6BLI).

Figure 3-24. SAMA5D24/BGA256/LPDDR1-SDRAM Layer 6

The layout example in the above figure shows layer 6 of the layout centered on the LPDDR1-SDRAM set. On this layer, the data lane 3 (D24-D31) signals have been routed, with the commented trace width and clearance, in accordance with the general routing rules. The route length mismatch within the data lane is 17 mils, well below the maximum 50 mils mismatch.

Figure 3-25. SAMA5D24/BGA256/LPDDR1-SDRAM Layer 8 (Bottom)

The above figure shows the bottom layer of the test board, centered on the LPDDR1-SDRAM device with the indicated trace width and clearance.

Figure 3-26. SAMA5D24/BGA256/LPDDR1-SDRAM Layer 5

Layer 5 of the test board serves as a power plane and is also used as an impedance matching reference for the neighboring signal layers (layers 4 and 6). The highlighted region shown in the above figure powers the SDRAM device. It covers a large surface and it does not feature any splits over any high-speed signal, in order to ensure a good signal integrity.