26.7.8 Peripheral Interrupt Flag Status – Bridge C

These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to these bits has no effect.

Writing a ‘1’ to these bits will clear the corresponding INTFLAGx interrupt flag.

Name:	INTFLAGC
Offset:	0x1C
Reset:	0x00000000
Property:	–


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
						TRNG
Access						RW
Reset						0


Bit	7	6	5	4	3	2	1	0
	AC	CCL		SERCOM3	SERCOM2		AES	QSPI
Access	RW	RW		RW	RW		RW	RW
Reset	0	0		0	0		0	0

Bit 10 – TRNG Interrupt Flag for TRNG

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the TRNG and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the TRNG interrupt flag.

Bit 7 – AC Interrupt Flag for AC

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the AC and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the AC interrupt flag.

Bit 6 – CCL Interrupt Flag for CCL

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the CCL and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the CCL interrupt flag.

Bit 4 – SERCOM3 Interrupt Flag for SERCOM3

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the SERCOM3 and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the SERCOM3 interrupt flag.

Bit 3 – SERCOM2 Interrupt Flag for SERCOM2

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the SERCOM2 and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the SERCOM2 interrupt flag.

Bit 1 – AES Interrupt Flag for AES

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the AES and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the AES interrupt flag.

Bit 0 – QSPI Interrupt Flag for QSPI

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the QSPI and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the QSPI interrupt flag.

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