26.7.6 Peripheral Interrupt Flag Status – Bridge A

These flags are set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGx bit, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ to these bits has no effect.

Writing a ‘1’ to these bits will clear the corresponding INTFLAGx interrupt flag.

Name: INTFLAGA
Offset: 0x14
Reset: 0x00000000
Property: 

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     TCC2TCC1TCC0TC3 
Access RWRWRWRW 
Reset 0000 
Bit 76543210 
 TC2TC1TC0SERCOM1SERCOM0EICFREQMPAC 
Access RWRWRWRWRWRWRWRW 
Reset 00000000 

Bit 11 – TCC2 Interrupt Flag for TCC2

This bit is set when a Peripheral Access Error occurs while accessing the TCC2, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 10 – TCC1 Interrupt Flag for TCC1

This bit is set when a Peripheral Access Error occurs while accessing the TCC1, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 9 – TCC0 Interrupt Flag for TCC0

This bit is set when a Peripheral Access Error occurs while accessing the TCC0, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 8 – TC3 Interrupt Flag for TC3

This bit is set when a Peripheral Access Error occurs while accessing the TC3, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 7 – TC2 Interrupt Flag for TC2

This bit is set when a Peripheral Access Error occurs while accessing the TC2, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 6 – TC1 Interrupt Flag for TC1

This bit is set when a Peripheral Access Error occurs while accessing the TC1, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 5 – TC0 Interrupt Flag for TC0

This bit is set when a Peripheral Write Access Error occurs while accessing the TC0, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 4 – SERCOM1 Interrupt Flag for SERCOM1

This bit is set when a Peripheral Access Error occurs while accessing the SERCOM1, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 3 – SERCOM0 Interrupt Flag for SERCOM0

This bit is set when a Peripheral Access Error occurs while accessing the SERCOM0, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 2 – EIC Interrupt Flag for EIC

This bit is set when a Peripheral Access Error occurs while accessing the EIC, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 1 – FREQM Interrupt Flag for FREQM

This bit is set when a Peripheral Access Error occurs while accessing the FREQM, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.

Bit 0 – PAC Interrupt Flag for PAC

This bit is set when a Peripheral Write Access Error occurs while accessing the PAC, and will generate an interrupt request if SET.ERR is ‘1’.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the flag.