26.7.5 Bridge Interrupt Flag Status

These flags are cleared by writing a ‘1’ to the corresponding bit.

These flags are set when an access error is detected by the corresponding AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Name: INTFLAGAHB
Offset: 0x10
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     PUKCCQSPIPBPICBPBCB 
Access RWRWRWRW 
Reset 0000 
Bit 76543210 
 PBBBPBABPFLASHCFLASHSRAM3SRAM2SRAM1SRAM0 
Access RWRWRWRWRWUURW 
Reset 00000000 

Bit 11 – PUKCC Interrupt Flag for PUKCC

This flag is set when an access error is detected by the PUKCC AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the PUKCC interrupt flag.

Bit 10 – QSPI Interrupt Flag for QSPI

This flag is set when an access error is detected by the QSPI AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the QSPI interrupt flag.

Bit 9 – PBPICB Interrupt Flag for PBPICB (PB-PIC-Bridge)

This flag is set when an access error is detected by the PBPICB AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the PBPICB interrupt flag.

Bit 8 – PBCB Interrupt Flag for PBCB (PB-Bridge-C)

This flag is set when an access error is detected by the PBCB AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the PBCB interrupt flag.

Bit 7 – PBBB Interrupt Flag for PBBB (PB-Bridge-B)

This flag is set when an access error is detected by the PBBB AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the PBBB interrupt flag.

Bit 6 – PBAB Interrupt Flag for HPB1 (PB-Bridge-A)

This flag is set when an access error is detected by the PBAB AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the PBAB interrupt flag.

Bit 5 – PFLASH Interrupt Flag for PFLASH (Peripheral Flash)

This flag is set when an access error is detected by the PFLASH AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the PFLASH interrupt flag.

Bit 4 – CFLASH Interrupt Flag for CFLASH (CPU Flash)

This flag is set when an access error is detected by the CFLASH AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the CFLASH interrupt flag.

Bit 3 – SRAM3 Interrupt Flag for SRAM3

This flag is set when an access error is detected by the SRAM3 AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the SRAM3 interrupt flag.

Bit 2 – SRAM2 Interrupt Flag for SRAM2

This flag is set when an access error is detected by the SRAM2 AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the SRAM2 interrupt flag.

Bit 1 – SRAM1 Interrupt Flag for SRAM1

This flag is set when an access error is detected by the SRAM1 AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the SRAM1 interrupt flag.

Bit 0 – SRAM0 Interrupt Flag for SRAM0

This flag is set when an access error is detected by the SRAM0 AHB Subordinate, and will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.

Writing a ‘0’ has no effect.

Writing a ‘1’ to this bit will clear the SRAM0 interrupt flag.