26.7.7 Peripheral Interrupt Flag Status – Bridge B
These flags are set when a Peripheral Access Error occurs while accessing the peripheral
associated with the respective INTFLAGx bit, and will generate an interrupt request if
INTENCLR/SET.ERR is ‘1’.
Writing a ‘0’ to these bits has no effect.
Writing a ‘1’ to these bits will clear the corresponding INTFLAGx
interrupt flag.
| Name: | INTFLAGB |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RAMECC | EVSYS | DMAC | DSU | ||||||
| Access | RW | RW | RW | RW | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 4 – RAMECC Interrupt Flag for RAMECC
This flag is set when a Peripheral Access Error occurs while accessing the RAMECC,
and will generate an interrupt request if INTENCLR/SET.ERR is
‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the RAMECC interrupt flag.
Bit 3 – EVSYS Interrupt Flag for EVSYS
This flag is set when a Peripheral Access Error occurs while accessing the EVSYS, and
will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the EVSYS interrupt flag.
Bit 2 – DMAC Interrupt Flag for DMAC
This flag is set when a Peripheral Access Error occurs while accessing the DMAC, and
will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the DMAC interrupt flag.
Bit 0 – DSU Interrupt Flag for DSU
This flag is set when a Peripheral Access Error occurs while accessing the DSU, and
will generate an interrupt request if INTENCLR/SET.ERR is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the DSU interrupt flag.