18.4.5 Permission Group Configuration

All bits in this register are writable only when CFGCON0.PGLOCK = 0.

There is no Flash location for this register because the purpose of this register is to provide a software-based protection mechanism to a device memory-mapped region, which is typically handled by a trusted boot/OScode.

Note: Ensure this register is programmed to the values shown: 0xE040_004C if you are not using Microchip-provided boot code.

Name:	CFGPGQOS
Offset:	0x50
Reset:	0xe040004c
Property:	-


Bit	31	30	29	28	27	26	25	24
	WISIBQOS[1:0]		FCQOS[1:0]				DSUPG[1:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L			R/W/L	R/W/L
Reset	1	1	1	0			0	0


Bit	23	22	21	20	19	18	17	16
	ICMQOS[1:0]		ICMPG[1:0]		ADCQOS[1:0]		ADCPG[1:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	1	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
							DMAPG[1:0]
Access							R/W/L	R/W/L
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	ICDJQOS[1:0]		ICDJPG[1:0]		CPUQOS[1:0]		CPUPG[1:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	1	0	0	1	1	0	0

Bits 31:30 – WISIBQOS[1:0] Wireless SIB QOS Control bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Value	Description
00	Disable; Background
01	Low; Sensitive bandwidth
10	Medium; Sensitive latency
11	High; Critical latency

Bits 29:28 – FCQOS[1:0] FC Controller QOS Control bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Value	Description
00	Disable; Background
01	Low; Sensitive bandwidth
10	Medium; Sensitive latency
11	High; Critical latency

Bits 25:24 – DSUPG[1:0] DSU Permission Group, drive the inputs cfg_dsu_pg[1:0] directly to the SSX

The DSU bus host has access to Access Controlled memory regions as defined by the bit-fields RDPER[3:0] and WRPER[3:0] in the Bus Structure’s Permission Groups SFRs for these memory regions. The encoding works as follows:

DSUPG[1:0] == 2’b11 : Read Access if RDPER[3]==1, Write Access if WRPER[3]==1 (Perm. Grp. 3)
DSUPG[1:0] == 2’b10 : Read Access if RDPER[2]==1, Write Access if WRPER[2]==1 (Perm. Grp. 2)
DSUPG[1:0] == 2’b01 : Read Access if RDPER[1]==1, Write Access if WRPER[1]==1 (Perm. Grp. 1)
DSUPG[1:0] == 2’b00 : Read Access if RDPER[0]==1, Write Access if WRPER[0]==1 (Perm. Grp. 0)

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 23:22 – ICMQOS[1:0] ICM QOS Control bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Value	Description
00	Disable; Background
01	Low; Sensitive bandwidth
10	Medium; Sensitive latency
11	High; Critical latency

Bits 21:20 – ICMPG[1:0] ICM Permission Group, drive the inputs cfg_icm_pg[1:0] directly to the SSX

The ICM bus host has access to Access Controlled memory regions as defined by the bit-fields RDPER[3:0] and WRPER[3:0] in the Bus Structure’s Permission Groups SFRs for these memory regions. The encoding works as follows:

ICMPG[1:0] == 2’b11 : Read Access if RDPER[3]==1, Write Access if WRPER[3]==1 (Perm. Grp. 3)
ICMPG[1:0] == 2’b10 : Read Access if RDPER[2]==1, Write Access if WRPER[2]==1 (Perm. Grp. 2)
ICMPG[1:0] == 2’b01 : Read Access if RDPER[1]==1, Write Access if WRPER[1]==1 (Perm. Grp. 1)
ICMPG[1:0] == 2’b00 : Read Access if RDPER[0]==1, Write Access if WRPER[0]==1 (Perm. Grp. 0)

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 19:18 – ADCQOS[1:0] ADC Controller QOS Control bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Value	Description
00	Disable; Background
01	Low; Sensitive bandwidth
10	Medium; Sensitive latency
11	High; Critical latency

Bits 17:16 – ADCPG[1:0] ADC Controller Permission Group, drive the inputs cfg_adc_pg[1:0] directly to the SSX

The ADC bus host has access to Access Controlled memory regions as defined by the bit-fields RDPER[3:0] and WRPER[3:0] in the Bus Structure’s Permission Groups SFRs for these memory regions. The encoding works as follows:

ADCPG[1:0] == 2’b11 : Read Access if RDPER[3]==1, Write Access if WRPER[3]==1 (Perm. Grp. 3)
ADCPG[1:0] == 2’b10 : Read Access if RDPER[2]==1, Write Access if WRPER[2]==1 (Perm. Grp. 2)
ADCPG[1:0] == 2’b01 : Read Access if RDPER[1]==1, Write Access if WRPER[1]==1 (Perm. Grp. 1)
ADCPG[1:0] == 2’b00 : Read Access if RDPER[0]==1, Write Access if WRPER[0]==1 (Perm. Grp. 0)

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 9:8 – DMAPG[1:0] DMA (Rd/Wr) Permission Group, drive the inputs cfg_dma_pg[1:0] directly to the SSX

The DMA bus host has access to Access Controlled memory regions as defined by the bit-fields RDPER[3:0] and WRPER[3:0] in the Bus Structure’s Permission Groups SFRs for these memory regions. The encoding works as follows:

DMAPG[1:0] == 2’b11 : Read Access if RDPER[3]==1, Write Access if WRPER[3]==1 (Perm. Grp. 3)
DMAPG[1:0] == 2’b10 : Read Access if RDPER[2]==1, Write Access if WRPER[2]==1 (Perm. Grp. 2)
DMAPG[1:0] == 2’b01 : Read Access if RDPER[1]==1, Write Access if WRPER[1]==1 (Perm. Grp. 1)
DMAPG[1:0] == 2’b00 : Read Access if RDPER[0]==1, Write Access if WRPER[0]==1 (Perm. Grp. 0)

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 7:6 – ICDJQOS[1:0] ICD-JTAG Bus QOS Control bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Value	Description
00	Disable; Background
01	Low; Sensitive bandwidth
10	Medium; Sensitive latency
11	High; Critical latency

Bits 5:4 – ICDJPG[1:0] ICD-JTAG Permission Group, drive the inputs cfg_icdj_pg[1:0] directly to the SSX

The ICD-JTAG bus host has access to Access Controlled memory regions as defined by the bit-fields RDPER[3:0] and WRPER[3:0] in the Bus Structure’s Permission Groups SFRs for these memory regions. The encoding works as follows:

ICDJPG[1:0] == 2’b11 : Read Access if RDPER[3]==1, Write Access if WRPER[3]==1 (Perm. Grp. 3)
ICDJPG[1:0] == 2’b10 : Read Access if RDPER[2]==1, Write Access if WRPER[2]==1 (Perm. Grp. 2)
ICDJPG[1:0] == 2’b01 : Read Access if RDPER[1]==1, Write Access if WRPER[1]==1 (Perm. Grp. 1)
ICDJPG[1:0] == 2’b00 : Read Access if RDPER[0]==1, Write Access if WRPER[0]==1 (Perm. Grp. 0)

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Bits 3:2 – CPUQOS[1:0] CPU I/D and System Bus QOS Control bits

Note: This field is only writable when CFGCON0.PGLOCK = 0.

Value	Description
00	Disable; Background
01	Low; Sensitive bandwidth
10	Medium; Sensitive latency
11	High; Critical latency

Bits 1:0 – CPUPG[1:0] CPU (Code) Permission Group, drive the inputs cfg_cpu_pg[1:0] directly to the SSX

The CPU Bus host has access to Access Controlled memory regions as defined by the bit fields RDPER[3:0] and WRPER[3:0] in the Bus Structure’s Permission Groups SFRs for these memory regions. The encoding works as follows:

CPUPG[1:0] == 2’b11 : Read Access if RDPER[3]==1, Write Access if WRPER[3]==1 (Perm. Grp. 3)
CPUPG[1:0] == 2’b10 : Read Access if RDPER[2]==1, Write Access if WRPER[2]==1 (Perm. Grp. 2)
CPUPG[1:0] == 2’b01 : Read Access if RDPER[1]==1, Write Access if WRPER[1]==1 (Perm. Grp. 1)
CPUPG[1:0] == 2’b00 : Read Access if RDPER[0]==1, Write Access if WRPER[0]==1 (Perm. Grp. 0)

Note:

CPUPG[1:0] automatically reverts to 2’b00 when the CPU acknowledges entering into an NMI exception as indicated by its STAUS[NMI] bit, which is carried by the cpu1_si_nmitaken system signal.
This field is only writable when CFGCON0.PGLOCK = 0.

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