18.4.3 Configuration Control Register 2

This register is loaded with trusted data from FBCFG3 during pre-boot period. Thereafter, it is controlled as described above.

Trusted data from Flash means when there is no BCFG* fail status during Flash configuration word reads. If accompanied by fail status or blank/erase indication then reset values (described in the register description below) are retained and new values from FBCFG3 are not loaded.

Name:	CFGCON2(L)
Offset:	0x20
Reset:	0x00
Property:	-


Bit	31	30	29	28	27	26	25	24
	DMTEN	DMTCNT[4:0]					WINSZ[1:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	1	1	1	1	1	1	1


Bit	23	22	21	20	19	18	17	16
	WDTEN	WINDIS	WDTSPGM	WDTPSR[4:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	1	1	1	1	1	1	1


Bit	15	14	13	12	11	10	9	8
	FSCMEN	CKSWEN	WAKE2SPD	SOSCSEL	WDTRMCS[1:0]		POSCMD[1:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	1	1	1	1	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	PMUTEST_VDD_EN		DMTINTV[2:0]			ACMP_CYCLE[2:0]
Access	R/W/L		R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0		1	1	1	0	0	0

Bit 31 – DMTEN Dead Man Timer Enable bit

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	DMT is enabled
0	DMT is disabled (control is placed on the DMTCON.ON bit)

Bits 30:26 – DMTCNT[4:0] Dead Man Timer Count Select bits

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
On devices where the DMTCNT[4:0] configuration field is loaded.

Value	Description
00000	Counter value is 2^8 for cfg_dmt_cnt[31:0]
00001	Counter value is 2^9 for cfg_dmt_cnt[31:0]
...	...
10100	Counter value is 2^28 for cfg_dmt_cnt[31:0]
10101	Counter value is 2^29 for cfg_dmt_cnt[31:0]
10110	Counter value is 2^30 for cfg_dmt_cnt[31:0]
10111	Counter value is 2^31 for cfg_dmt_cnt[31:0]
11000 - 11111	Reserved

Bits 25:24 – WINSZ[1:0] Watchdog Timer Window Size bits

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
00	Window size is 75%
01	Window size is 50%
10	Window size is 37.5%
11	Window size is 25%

Bit 23 – WDTEN Watchdog Timer Enable bit

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	WDT is enabled
0	WDT is disabled (control is placed on the SWDTEN bit)

Bit 22 – WINDIS Windowed Watchdog Timer Disable bit

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Standard WDT is selected; windowed WDT disabled
0	Windowed WDT is enabled

Bit 21 – WDTSPGM Watchdog Timer Stop during Flash Programming bit

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	The WDT stops during NVR programming (legacy)
0	The WDT runs during NVR programming (for read/execute while programming Flash systems)

Bits 20:16 – WDTPSR[4:0] Watchdog Timer Post-scale Select Run bits

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
10100	1:1048576
10011	1:524288
10010	1:262144
10001	1:131072
10000	1:65536
01111	1:32768
01110	1:16384
01101	1:8192
01100	1:4096
01011	1:2048
01010	1:1024
01001	1:512
01000	1:256
00111	1:128
00110	1:64
00101	1:32
00100	1:16
00011	1:8
00010	1:4
00001	1:2
00000	1:1

Bit 15 – FSCMEN Fail-Safe Clock Monitor Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	FSCM enabled
0	FSCM disabled

Bit 14 – CKSWEN Software Clock Switching Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Software clock switching is enabled
0	Software clock switching is disabled

Bit 13 – WAKE2SPD 2-Speed startup enabled in Sleep mode bit

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	When the device exits the Sleep mode, the SYS_CLK will be from FRC until the selected clock is ready.
0	Not applicable.

Bit 12 – SOSCSEL SOSC Selection Configuration bit

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Crystal (SOSCI/SOSCO) mode is selected
0	Digital (SCLKI) mode is selected

Bits 11:10 – WDTRMCS[1:0] WDT RUN Mode Clock Select

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’ or ‘10’.

Value	Description
11	LPRC
10	Do not use
01	Do not use
00	Module PB Clock

Bits 9:8 – POSCMD[1:0] Primary Oscillator Configuration bits

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
11	Primary oscillator is disabled
10	HS oscillator mode is selected
01	HS oscillator mode is selected
00	HS oscillator mode is selected

Bit 7 – PMUTEST_VDD_EN PMU Test Output or VDD/2 Enable via ADC IE12

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	PMU test output monitor is enabled
0	VDD/2 monitor is enabled

Bits 5:3 – DMTINTV[2:0] Dead Man Timer Count Window Interval bits

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
000	Window/Interval value is zero for cfg_dmt_intv[31:0] - windowed mode is disabled
001	Window/Interval value is 1/2 Counter value for cfg_dmt_intv[31:0]
010	Window/Interval value is 3/4 Counter value for cfg_dmt_intv[31:0]
011	Window/Interval value is 7/8 Counter value for cfg_dmt_intv[31:0]
100	Window/Interval value is 15/16 Counter value for cfg_dmt_intv[31:0]
101	Window/Interval value is 31/32 Counter value for cfg_dmt_intv[31:0]
110	Window/Interval value is 63/64 Counter value for cfg_dmt_intv[31:0]
111	Window/Interval value is 127/128 Counter value for cfg_dmt_intv[31:0]

Bits 2:0 – ACMP_CYCLE[2:0] AC SIB Comparator Result Wait Cycles

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
n	Wait for 32µs* ACMP_CYCLE+1 cycles to generate comparator done indication