58.6.8.4.3 Memory Array Access

To access the memory array, QSPI_IFR.TFRTYP must be set to ‘1’. In the case of write access to the memory array, QSPI_IFR.TFRTYP can be set to ‘0’ with QSPI_IFR.SMRM set to ‘1’.

  • TFRTYP = 0 and SMRM = 1

This configuration is allowed for write memory array access only (read access to the memory array is not supported in this configuration). When QSPI_IFR.SMRM is set to ‘1’, accesses to the memory are triggered and controlled by QSPI registers. QSPI_IAR.ADDR must be configured with the address of the first data to write if the frame contains an address field, this field is the one used for the instruction frame address field. The QSPI_IFR.APBTFRTYP must be set to ‘0’. Write frames are triggered writing the QSPI_TDR register. Each time a new transfer trigger is issued, an SPI transfer is performed with a byte size or halfword size if QSPI_IFR.WIDTH field is configured to OCT_OUTPUT, OCT_IO or OCT_CMD and QSPI_IFR.DDREN=1. Another byte or halfword is written each time QSPI_TDR is written (flag TDRE shows when a new data can be written). If a data is not consecutive to the previously sent data, a new frame must be issued. The SPI transfer ends by writing QSPI_CR.LASTXFER. See Figure 58-14 for details.

  • TFRTYP = 1

When QSPI_IFR.TFRTYP is set to ‘1’, accesses to the memory are triggered by performing an access in the QSPI memory space. The address of the instruction frame is defined by the address of the first data access in the QSPI memory space. Each time the accesses become nonsequential (addresses are not consecutive), a new instruction frame is sent with the last system bus access address. This way, the system can read/write data at a random location in the serial memory. QSPI_WRACNT.NBWRA generates a rising flag when a given number of bytes have been sent to the memory. QSPI_ISR.LWRA indicates the transmission of the last byte. The NBWRA internal counter is reset and begins counting after each start of instruction frame except when QSPI_IFR.PROTTYP = ‘3’ and QSPI_IFR.HFWBEN = 1 where the NBWRA counter is reset after setting the QSPI_IFR.HFWBEN bit to ‘1’ and counts data on every frame.

In the case of read accesses to the memory array, QSPI_SR.RBUSY must be at ‘0’ before terminating the frame. The last SPI transfer ends by writing QSPI_CR.LASTXFER. See Figure 58-15 and Figure 58-16 for details.

The following figures illustrate instruction transmission management.

Figure 58-12. Instruction Transmission Flow Diagram SMRM = 1 and TFRTYP = 0 (Memory Register Access)
Figure 58-13. Instruction Transmission Flow Diagram SMRM = 0 and TFRTYP = 0 (Memory Register Access)
Figure 58-14. Instruction Transmission Flow Diagram SMRM = 1 and TFRTYP = 0 (Memory Write Access)
Figure 58-15. Instruction Transmission Flow Diagram TFRTYP = 1, Memory Write Access
Figure 58-16. Instruction Transmission Flow Diagram TFRTYP = 1, Memory Read Access
Figure 58-17. HyperFlash “Write Buffer” Flow Diagram SMRM = 1 and TFRTYP = 0 (Memory Write Access)
Figure 58-18. HyperFlash “Write Buffer” Flow Diagram TFRTYP = 1, Memory Write Access