67.6.6 GMAC Timings

Timings are provided in the following conditions:
  • 1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV = 1, SR = 0
  • 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV = 0, SR = 0
Figure 67-26. Ethernet MAC MDIO Interface Timings Characteristics
Table 67-26. Ethernet MAC Signals Relative to MDC (MDIO Mode)
Symbol Parameters Min Max Unit
GMAC1 MDIO input data setup time before MDC rising edge 10 – ns
GMAC2 MDIO input data hold time after MDC rising edge 10 – ns
GMAC3 MDC falling edge to MDIO output data valid 0 25 ns
Figure 67-27. Ethernet MAC RMII Mode Timing Diagram
Table 67-27. Ethernet MAC RMII Mode Timing Characteristics
Symbol Parameters Conditions Min Typ Max Unit
GMAC21 TXEN toggling from REFCK rising – 2 – 16 ns
GMAC22 TX[1:0] toggling from REFCK rising – 2 – 16 ns
GMAC23 Setup for RX[1:0] from REFCK rising – 4 – – ns
GMAC24 Hold for RX[1:0] from REFCK rising – 2 – – ns
GMAC25 Setup for RXER from REFCK rising – 4 – – ns
GMAC26 Hold for RXER from REFCK rising – 2 – – ns
GMAC27 Setup for CRSDV from REFCK rising – 4 – – ns
GMAC28 Hold for CRSDV from REFCK rising – 2 – – ns
Figure 67-28. Ethernet MAC RGMII Timing Diagram
Table 67-28. Ethernet MAC RGMII Mode Timing Characteristics
Symbol Parameter Min Max Unit
GMAC29 TXCTL toggling from TXCK edge -500 500 ps
GMAC30 TXD[3:0] toggling from TXCK edge -500 500 ps
GMAC31 RXD[3:0] Setup time before RXCK edge 1.0 – ns
GMAC32 RXD[3:0] Hold time after RXCK edge 1.0 – ns
GMAC33 RXCTL Setup time before RXCK edge 1.0 – ns
GMAC34 RXCTL Hold time after RXCK edge 1.0 – ns