67.6.1 MPDDRC Characteristics

The MPDDRC is compliant with the following JEDEC standards:

  • DDR3-SDRAM: JESD79-3C with operating frequencies up to 266 MHz
  • DDR3L-SDRAM: JESD79-3-1A with operating frequencies up to 266 MHz
  • DDR2-SDRAM: JESD79-2F with operating frequencies up to 266 MHz

The physical interface (PCB layout) between the processor and its memory has a major impact on the signal integrity. Microchip provides IBIS models of the SAM9X7 Series device and strongly recommends verifying this processor-memory interface on a PCB simulation tool. For design guidance, refer to the Microchip application note “'SAM9X75 Hardware Design Considerations” (AN4962), available on www.microchip.com.

The following table provides the recommended settings on the MPDDRC_RD_DATA_PATH.SHIFT_SAMPLING field depending on the memory type and on its operating frequency.

Table 67-21. SHIFT_SAMPLING Settings
SDRAM Type SDRAM Clock Frequency (MHz) SHIFT_SAMPLING
DDR2-SDRAM 125 ≤ fSDRAM_CLK ≤ 266 1
DDR3(L)-SDRAM (DLL on) fSDRAM_CLK = 266 3
DDR3(L)-SDRAM (DLL off) fSDRAM_CLK ≤ 200 3