10.1.4 Minimum Delay Analysis with Timing Analyzer - 32-Bit Shift Register Example
The SmartTime Minimum Delay Analysis window identifies any hold violations that exist in the design.
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From the SmartTime Analysis window, choose Tools > Minimum Delay
Analysis.
The Minimum Delay Analysis View appears, as shown in the following figure.
- Expand my_clk to display Register to Register, External Hold, Clock to Output, Register to Asynchronous, External Removal, and Asynchronous to Register path sets.
-
Click Register to Register to display the reg to reg
paths.
The window displays a list of register to register paths and detailed timing analysis for the selected path. All the slack value are positive, indicating that there are no hold time violations.
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Click to select the first path and observe the hold analysis calculation
details, as shown in the following figure.