6.3 Maximum Delay Analysis View

To enter Maximum Delay Analysis View:
  1. In the Domain Browser, select the clock domain. Clock domains with a
    ???
    indicate that the timing requirements in these domains were met. Clock domains with an x indicate that there are violations within these domains. Paths List shows the timing paths sorted by slack. The path with the lowest slack (biggest violation) is at the top of the list.
  2. Select the path you want to view.
    Path Details below the Paths List shows detailed information about how the slack was computed by detailing the arrival time and required time calculation. If a path is violated, the slack is negative and shown in red.
  3. To display a separate view that includes the path details and schematic, double-click the path.
  4. Repeat this procedure as necessary.
    Note: If the minimum pulse width of one element on the critical path limits the maximum frequency for the clock, an icon for the clock name appears in the Summary List. Clicking the icon displays the name of the pin that limits the clock frequency.