25.7.5 Bridge Interrupt Flag Status

These flags are cleared by writing a ‘1’ to the corresponding bit.

These flags are set when an access error is detected by the corresponding AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Name:	INTFLAGAHB
Offset:	0x10
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
			PBDB	CRYPTO	RoT	QSPI	PBPICB	PBCB
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PBBB	PBAB	PFLASH	CFLASH	SRAM4	SRAM3	SRAM2	SRAM1
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 13 – PBDB Interrupt Flag for PBDB (PB-Bridge-D)

This flag is set when an access error is detected by the PBDB AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the PBDB Interrupt flag.

Note: This register bit does not reflect accesses to reserved spaces between peripherals on the PB-Bridge-D bus; instead, such accesses are reflected in the INTFLAGD register. For more details, see INTFLAGD from Related Links.

Bit 12 – CRYPTO Interrupt Flag for Crypto

This flag is set when an access error is detected by the Crypto AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the Crypto Interrupt flag.

Bit 11 – RoT Interrupt Flag for RoT ROM

This flag is set when an access error is detected by the RoT ROM Client, and an interrupt request is generated if INTENCLR/SET.ERR is ‘1’.

Writing a 0 has no effect.

Writing a 1 to this bit clears the RoT Interrupt flag.

Bit 10 – QSPI Interrupt Flag for QSPI (Reserved for future use)

This flag is set when an access error is detected by the QSPI AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the QSPI Interrupt flag.

Bit 9 – PBPICB Interrupt Flag for PBPICB (PB-PIC-Bridge) (Reserved for future use)

This flag is set when an access error is detected by the PBPICB AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the PBPICB Interrupt flag.

Bit 8 – PBCB Interrupt Flag for PBCB (PB-Bridge-C)

This flag is set when an access error is detected by the PBCB Bridge AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the PBCB Interrupt flag.

Bit 7 – PBBB Interrupt Flag for PBBB (PB-Bridge-B)

This flag is set when an access error is detected by the PBBB Bridge AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the PBBB Interrupt flag.

Bit 6 – PBAB Interrupt Flag for PBAB (PB-Bridge-A)

This flag is set when an access error is detected by the PBAB Bridge AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the PBAB Interrupt flag.

Bit 5 – PFLASH Interrupt Flag for PFLASH (Peripheral Flash)

This flag is set when an access error is detected by the PFLASH AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the PFLASH Interrupt flag.

Bit 4 – CFLASH Interrupt Flag for CFLASH (CPU Flash)

This flag is set when an access error is detected by the CFLASH AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the CFLASH Interrupt flag.

Bit 3 – SRAM4 Interrupt Flag for SRAM4

This flag is set when an access error is detected by the SRAM4 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the SRAM4 Interrupt flag.

Bit 2 – SRAM3 Interrupt Flag for SRAM3

This flag is set when an access error is detected by the SRAM3 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the SRAM3 Interrupt flag.

Bit 1 – SRAM2 Interrupt Flag for SRAM2

This flag is set when an access error is detected by the SRAM2 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the SRAM2 Interrupt flag.

Bit 0 – SRAM1 Interrupt Flag for SRAM1

This flag is set when an access error is detected by the SRAM1 AHB Client, and an interrupt request is generated if INTENCLR/SET.ERR is 1.

Writing a 0 has no effect.

Writing a 1 to this bit clears the SRAM1 Interrupt flag.