25.7.3 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register can also be reflected in the Interrupt Enable Set register (INTENSET).
Name: INTENCLR
Offset: 0x08
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
        ERR 
Access RW 
Reset 0 

Bit 0 – ERR Peripheral Access Error Interrupt Disable

This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the Peripheral Access Error interrupt Enable bit and disables the corresponding interrupt request.

ValueDescription
0 Peripheral Access Error interrupt is disabled.
1 Peripheral Access Error interrupt is enabled.