25.7.11 Peripheral Write Protection Status - Bridge B
Writing to this register has no effect.
Reading the STATUS register returns peripheral write protection status:
| Value | Description |
|---|---|
| 0 | Peripheral is not write protected |
| 1 | Peripheral is write protected |
| Name: | STATUSB |
| Offset: | 0x38 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ETH | RAMECC | EVSYS | DMAC | DSU | |||||
| Access | RW | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 5 – ETH Interrupt flag for ETH
This flag is set when a Peripheral Access Error occurs while accessing the
Ethernet, and will generate an interrupt request if INTENCLR/SET.ERR is
‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the ETH interrupt flag.
Bit 4 – RAMECC RAMECC APB Protect Enable
| Value | Description |
|---|---|
| 0 | RAMECC peripheral is not write protected |
| 1 | RAMECC peripheral is write protected |
Bit 3 – EVSYS EVSYS APB Protect Enable
| Value | Description |
|---|---|
| 0 | EVSYS peripheral is not write protected |
| 1 | EVSYS peripheral is write protected |
Bit 2 – DMAC DMAC APB Protect Enable
| Value | Description |
|---|---|
| 0 | DMAC peripheral is not write protected |
| 1 | DMAC peripheral is write protected |
Bit 0 – DSU DSU APB Protect Enable
| Value | Description |
|---|---|
| 0 | DSU peripheral is not write protected |
| 1 | DSU peripheral is write protected |