37.8.3 Low-Power Mode

The ADC core can be placed in a low-power state by disabling the digital circuit for individual ADC cores that are not running. This is possible by clearing the DIGEN7 bit in the ADCCON3 register. (See ADCCON3 register from Related Links.)

An even lower power state is possible by disabling the analog and bias circuit for ADC core that is not running. This is possible by clearing the ANEN7 bit in the ADCANCON register. (See ADCANCON register from Related Links.) Disabling the digital circuit to achieve Low-Power mode provides a significantly faster module restart compared to disabling and re-enabling the analog and bias circuit of the ADC core. This is because disabling and re-enabling the analog and bias circuit using the ANEN7 bit requires a wake-up time (typical minimum wake-up time of 20 µs) for the ADC core before it can be used. See Electrical Characteristics from Related Links for more information on the stabilization time.

When the analog and bias circuit for an ADC core is enabled, the wake-up must be polled (or through an interrupt) using the wake-up ready bits, WKRDY7, which must be equal to 1.