16.21.5 NVMDATAx – Flash Program Data Register x
Note: These bits are only reset by a POR and are not affected by
other Reset sources.
| Name: | NVMDATAx |
| Offset: | 0x40 + x*0x10 [x=0..7] |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NVMDATA[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NVMDATA[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NVMDATA[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NVMDATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – NVMDATA[31:0] Flash Programming Data x bits (x=0...7)
The value in this register is written to Flash when a program operation is commanded.
- Single Double Word
Program (64-bit)
- Writes NVMDATA0 to the target Flash address defined in NVMADDR]31:3]
- Writes NVMDATA1 to the target Flash address defined in NVMADDR[31:3]
- Quad Double Word Program
(256-bit)
- Writes NVMDATA0 to NVMADDR[31:5], and bits [4:2]=000
- Writes NVMDATA1 to NVMADDR[31:5], and bits [4:2]=001
- Writes NVMDATA2 to NVMADDR[31:5], and bits [4:2]=010
- Writes NVMDATA3 to NVMADDR[31:5], and bits [4:2]=011
- Writes NVMDATA4 to NVMADDR[31:5], and bits [4:2]=100
- Writes NVMDATA5 to NVMADDR[31:5], and bits [4:2]=101
- Writes NVMDATA6 to NVMADDR[31:5], and bits [4:2]=110
- Writes NVMDATA7 to NVMADDR[31:5], and bits [4:2]=111
Note:
- Hardware prevents writes to this register when NVMCON.NVMWR =
1.