16.21.4 NVMADDR – Flash Address Register

Name:	NVMADDR
Offset:	0x30
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	NVMADDR[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	NVMADDR[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	NVMADDR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	NVMADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – NVMADDR[31:0] Flash (Word) Address bits

Note: These bits are only reset by a POR and are not affected by other Reset sources.

Table 16-5. Flash (Word) Address Bits
NVMOP	Flash Address Bits
Page Erase	Address identifies the page to erase Any address within a 4 Kbytes page boundary will cause the page to be erased
Row program	Address identifies the row to program The value of the address must be aligned to a row boundary
Double Word Program	64-bit Word on 256-bit flash system Address identifies the Double Word to program NVMADDR[2:0] bits are ignored Must be aligned to a Double Word boundary
Quad Double Word Program	256-bit Word on 256-bit flash system) Address identifies the Quad Double Word to program NVMADDR[4:0] bits are ignored Must be aligned to a Quad Double Word boundary

Note:

Hardware prevents writes to this register when NVMCON.WR = 1.
For all other NVMOP[3:0] bit settings, the Flash address is ignored. For additional information on these bits, see the NVMCON register from Related Links.

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