16.21.1 NVMCON - Programming Control Register

Note:
  1. See NVMPWPLT and NVMPWPGTE for program space write protection conditions for the operation used in NVMOP.

    See NVMLBWP for NVR space write protection conditions for the operation used in NVMOP.

  2. This operation is only allowed if test_detect_active is asserted else no operation occurs. No interrupt generated, WRERR not set.

    Only available to internal (CPU) sources. All NVR and PWP protection mechanisms are ignored.

  3. This operation is only allowed if test_private_mode is asserted else no operation occurs. No interrupt generated, WRERR not set. Only available to internal (CPU) sources. All NVR and PWP protection mechanisms are ignored.
  4. If cfg_flash_eccctl[1:0]=2’b00, this operation no operation occurs but does not affect WRERR or LVDERR.
  5. SRF is included in this erase. SRF substitution addresses stored in test flash are not affected by this erase.
  6. When Code Protected these NVMOP commands are dis-allowed and status does not change. (This protects against modifying user CP/SIGN settings or corrupting user code.)
  7. Behaves as R-0, when PFM_NUM_PANELS=1 or cfg_pfm_num_panels = 2’b10 or 2’b01.
  8. These bits are only reset by a POR and are not affected by other Reset sources.
Name: NVMCON
Offset: 0x00
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 WRWRENWRERRLVDERR     
Access R/S/HCR/WR/HS/HCR/HS/HC 
Reset 0000 
Bit 76543210 
     NVMOP[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 15 – WR Write Control Bit

Note: This field can only be modified when WREN = 1, TEMP = 1 and the NVMKEY unlock sequence is satisfied.
ValueDescription
1Initiate a Flash operation. Hardware clears this bit when the operation completes
0Flash operation complete or inactive

Bit 14 – WREN Write Enable Bit

ValueDescription
1Enables writes to WR
0Disables writes to WR

Bit 13 – WRERR  Write Error Bit(8)

Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR)
ValueDescription
1Program or erase sequence did not complete successfully
0Program or erase sequence completed normally

Bit 12 – LVDERR Low Voltage Detect Error Bit(8)

The error is only captured for programming/erase operations (when NVMWR = 1).
Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (NVMWR)
ValueDescription
1Low voltage is detected (possible data corruption if WRERR is set)
0Voltage level is within the acceptable range for programming

Bits 3:0 – NVMOP[3:0]  NVM Operation Bits(8)

These bits are only writable when WREN = 0.

ValueDescription
1111 Reserved
1110(2) Chip Erase Operation: Erases PFM, BFM (except configuration page) when accessed through SWD interface only
... ...
1000 Reserved
0111(5,6) Program erase operation: Erase all program Flash memory (PFM). All pages in this region must be unprotected for the erase operation to proceed.
0110(5,6)

Upper Program Flash Memory Erase Operation: Erases only the upper mapped region of the program Flash memory. All pages in this region must be unprotected for the erase operation to proceed. In the PIC32CX-BZ6, which has a single bank of Flash memory, this operation functions the same as when NVMOP is set to 0111.
0101(5,6)

Lower Program Flash Memory Erase Operation: Erases only the lower mapped region of the program Flash memory. All pages in this region must be unprotected for the erase operation to proceed. In the PIC32CX-BZ6, which has a single bank of Flash memory, this operation functions the same as when NVMOP is set to 0111.
0100(1,6) Page erase operation: Erases the page selected by NVMADDR if the page is not write-protected
0011(1,6) Row program operation: Programs row selected by NVMADDR if the page is not write-protected
0010(1,6) Quad Double Word (128-bit) program operation: Programs the 128-bit Flash Word selected by NVMADDR if the page is not write-protected
0001(1,4,6) Double Word program operation: Programs the Word selected by NVMADDR if the page is not write-protected(2)
0000Clear the status of WRERR and LVDERR