46.4.8 Position Counter Initialization Modes

By using the PIMOD<2:0> bits (QEIxCON<12:10>), the user application can specify how the position counter is initialized during the module operation.

• Mode0 – The position counter is unaffected by the index input.
• Mode1 –The position counter is cleared whenever an index input event is detected.
• Mode2 –The position counter is initialized with the contents of the QEIxICC register on the next detected index input event. When the index event occurs, the PIMOD<2:0> bits are cleared, and then the counter operates in Mode 0.
• Mode3 –The position counter is initialized with the contents of the QEIxICC register on the next detected index input event following the assertion of the home input. When an index event occurs following the home event, the PIMOD<2:0> bits are cleared, and then the counter operates in Mode 0.
• Mode4 –The position counter is initialized with the contents of the QEIxICC register on the second detected index input event following the assertion of the home input. When the second index event occurs following the home event, the PIMOD<2:0> bits are cleared, and then the counter operates in Mode 0.
• Mode5 –The position counter is cleared when the position counter value equals the QEIxICC register value.
• Mode6 –The position counter is loaded with the contents of the QEIxCMPL register when the position counter value equals the QEIxICC register value and a count up pulse is detected. The counter is loaded with the contents of the QEIxICC register when the position counter value equals the QEIxCMPL register value and a count down pulse is detected.
• Mode7 – Same as mode 6, with the additional feature of the position counter being cleared whenever an index input event is detected