46.4.2 Velocity Counter

The 32-bit wide Velocity Counter (VELxCNT) register increments or decrements based on the signal from the quadrature decoder logic. Reading this register resets the register. The index input or any of the modes specified by the PIMOD<2:0> bits (QEIxCON<12:10>) does not affect the operation of the velocity counter. If the velocity counter rolls over from 0x7FFFFFFF to 0x80000000, or from 0x80000000 to 0x7FFFFFFF, and the VELOVIEN bit (QEIxSTAT<4>) is set, an interrupt will be generated. The following figure illustrates the timing diagram of the Velocity Counter operation

Note: The velocity counter specifies the distance traveled between the time interval of each sample. Reading the VELxCNT register results in counter reset. The user application should read the velocity counter at a rate of 1 kHz to 4 kHz.
Figure 46-6. Velocity Counter