46.4.7 Index Event

The IMV<1:0> bits (QEIxCON<9:8>) specify the state of the QEA and QEB input signals required to acknowledge an index event. An index event is accepted when an index pulse occurs while the value of the QEA and QEB inputs match the condition set in the IMV<1:0> bits. This prevents further index events from being accepted until the index input signal is deasserted, and ensures that only one index event occurs for each index input pulse. Figure 46-8, on the previous page, illustrates the index reset position counter operation.