45.7.1 ETH Control A Register

Table 45-15. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CTRLA
Offset: 0x0000
Reset: 0x00000000
Property: PAC Write Protected

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  RUNSTDBY    ENABLESWRST 
Access R/WR/WR/S/HC 
Reset 000 

Bit 6 – RUNSTDBY Run in Standby

This bit is used to keep the ETH running in standby mode.

ValueDescription
0The ETH module is disabled in Standby Sleep mode, clock requests are de-asserted after any pending bus transactions or requests are complete.
1The ETH module continues to run in Standby Sleep mode.

Bit 1 – ENABLE ETH Clock Enable

Changing the state of this bit from ‘0’ to ‘1’ or ‘1’ to ‘0’ sets the SYNCBUSY.ENABLE bit to 1. The SYNCBUSY.ENABLE bit stays asserted until the module is either completely enabled or completely disabled.

Note: If the ETH is enabled the user should ensure the ETH finishes all tasks before writing this bit to ‘0’.
ValueDescription
0Disable module. System clock is only requested for bus transactions. GCLK is never requested, turn off module, disable clocks, disable interrupt event generation.
1Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests.

Bit 0 – SWRST Software Reset Busy bit

Synchronizing Busy bit for CTRLA.SWRST

This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.

This bit is set when the synchronization of SWRST bit between clock domains is started.

Note:
  1. When the CTRLA.SWRST is written, the user should poll SYNCB.SWRST bit to know when the reset operation is complete.
  2. During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.