2.8.1.1 Timing Characteristics

Table 2-86. SmartFusion CCC/PLL Specification
Parameter Minimum Typical Maximum Units
Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 — 350 MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 — 3501 MHz
Delay Increments in Programmable Delay Blocks2,3 — 1604 — ps
Number of Programmable Values in Each Programmable Delay Block — — 32
Input Period Jitter — — 1.5 ns
Acquisition Time — — — —
LockControl = 0 — — 300 µs
LockControl = 1 — — 6.0 ms
Tracking Jitter5 — — — —
LockControl = 0 1.6 ns
LockControl = 1 — — 0.8 ns
Output Duty Cycle 48.5 — 5.15 %
Delay Range in Block: Programmable Delay 12,3 0.6 — 5.56 ns
Delay Range in Block: Programmable Delay 22,3 0.025 — 5.56 ns
Delay Range in Block: Fixed Delay2,3 — 2.2 — ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT 6.7 Maximum Peak-to-Peak Period Jitter
SSO ≤ 2 SSO ≤ 4 SSO ≤ 8 SSO ≤ 16
FG/CS PQ FG/CS PQ FG/CS PQ FG/CS PQ
0.75 MHz to 50 MHz 0.5% 1.6% 0.9% 1.6% 0.9% 1.6% 0.9% 1.8%
50 MHz to 250 MHz 1.75% 3.5% 9.3% 9.3% 9.3% 17.9% 10.0% 17.9%
250 MHz to 350 MHz 2.5% 5.2% 13.0% 13.0% 13.0% 25.0% 14.0% 25.0%
Note:
  1. One of the CCC outputs (GLA0) is used as an MSS clock and is limited to 100 MHz (maximum) by software. Details regarding CCC/PLL are in the “PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators” chapter of the SmartFusion Microcontroller Subsystem User's Guide.
  2. This delay is a function of voltage and temperature. See Table 2-7 for deratings.
  3. TJ = 25 °C, VCC = 1.5V
  4. When the CCC/PLL core is generated by Microchip core generator software, not all delay values of the specified delay increments are available. Refer to SmartGen online help for more information.
  5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
  6. Measurement done with LVTTL 3.3V 12 mA I/O drive strength and High slew rate. VCC/VCCPLL = 1.425V, VCCI = 3.3V, 20 pF output load. All I/Os are placed outside of the PLL bank.
  7. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out within ± 200 ps of each other.
  8. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps.
Figure 2-38. Peak-to-Peak Jitter Definition
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.