2.9.1.2 Timing Characteristics

Table 2-87. RAM4K9 Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425V
Parameter	Description	–1	Std.	Units
t_AS	Address setup time	0.26	0.32	ns
t_AH	Address hold time	0.00	0.00	ns
t_ENS	REN, WEN setup time	0.15	0.18	ns
t_ENH	REN, WEN hold time	0.10	0.12	ns
t_BKS	BLK setup time	0.25	0.30	ns
t_BKH	BLK hold time	0.02	0.02	ns
t_DS	Input data (DIN) setup time	0.19	0.23	ns
t_DH	Input data (DIN) hold time	0.00	0.00	ns
t_CKQ1	Clock High to new data valid on DOUT (output retained, WMODE = 0)	1.89	2.27	ns
t_CKQ1	Clock High to new data valid on DOUT (flow-through, WMODE = 1)	2.49	2.99	ns
t_CKQ2	Clock High to new data valid on DOUT (pipelined)	0.95	1.13	ns
t_C2CWWH¹	Address collision clk-to-clk delay for reliable write after write on same address—applicable to rising edge	0.23	0.27	ns
t_C2CRWH¹	Address collision clk-to-clk delay for reliable read access after write on same address—applicable to opening edge	0.34	0.40	ns
t_C2CWRH¹	Address collision clk-to-clk delay for reliable write access after read on same address— applicable to opening edge	0.37	0.44	ns
t_RSTBQ	RESET Low to data out Low on DOUT (flow-through)	0.97	1.17	ns
t_RSTBQ	RESET Low to Data Out Low on DOUT (pipelined)	0.97	1.17	ns
t_REMRSTB	RESET removal	0.30	0.36	ns
t_RECRSTB	RESET recovery	1.59	1.90	ns
t_MPWRSTB	RESET minimum pulse width	0.23	0.26	ns
t_CYC	Clock cycle time	3.41	4.01	ns
F_MAX	Maximum clock frequency	293.08	249.12	MHz

Note:

For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs.
For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

Table 2-88. RAM512X18 Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425V
Parameter	Description	–1	Std.	Units
t_AS	Address setup time	0.26	0.32	ns
t_AH	Address hold time	0.00	0.00	ns
t_ENS	REN, WEN setup time	0.10	0.12	ns
t_ENH	REN, WEN hold time	0.06	0.07	ns
t_DS	Input data (WD) setup time	0.19	0.23	ns
t_DH	Input data (WD) hold time	0.00	0.00	ns
t_CKQ1	Clock High to new data valid on RD (output retained, WMODE = 0)	2.28	2.74	ns
t_CKQ2	Clock High to new data valid on RD (pipelined)	0.95	1.14	ns
t_C2CRWH¹	Address collision clk-to-clk delay for reliable read access after write on same address—applicable to opening edge	0.38	0.44	ns
t_C2CWRH¹	Address collision clk-to-clk delay for reliable write access after read on same address—applicable to opening edge	0.44	0.52	ns
t_RSTBQ	RESET Low to data out Low on RD (flow-through)	0.97	1.17	ns
t_RSTBQ	RESET Low to data out Low on RD (pipelined)	0.97	1.17	ns
t_REMRSTB	RESET removal	0.30	0.36	ns
t_RECRSTB	RESET recovery	1.59	1.90	ns
t_MPWRSTB	RESET minimum pulse width	0.23	0.26	ns
t_CYC	Clock cycle time	3.41	4.01	ns
F_MAX	Maximum clock frequency	293.08	249.12	MHz

Note:

For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs.
For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.