24.5.4 SUPC Wakeup Mode Register
Note: This register is located in the VDDIO domain.
| Name: | SUPC_WUMR |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LPDBC[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WKUPDBC[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LPDBCCLR | LPDBCEN1 | LPDBCEN0 | RTCEN | RTTEN | SMEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 18:16 – LPDBC[2:0] Low-power Debouncer Period
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Disables the low-power debouncers. |
| 1 | 2_RTCOUT | WKUP0/1 in active state for at least 2 RTCOUTx clock periods |
| 2 | 3_RTCOUT | WKUP0/1 in active state for at least 3 RTCOUTx clock periods |
| 3 | 4_RTCOUT | WKUP0/1 in active state for at least 4 RTCOUTx clock periods |
| 4 | 5_RTCOUT | WKUP0/1 in active state for at least 5 RTCOUTx clock periods |
| 5 | 6_RTCOUT | WKUP0/1 in active state for at least 6 RTCOUTx clock periods |
| 6 | 7_RTCOUT | WKUP0/1 in active state for at least 7 RTCOUTx clock periods |
| 7 | 8_RTCOUT | WKUP0/1 in active state for at least 8 RTCOUTx clock periods |
Bits 14:12 – WKUPDBC[2:0] Wakeup Inputs Debouncer Period
| Value | Name | Description |
|---|---|---|
| 0 | IMMEDIATE | Immediate, no debouncing, detected active at least on one Slow Clock edge. |
| 1 | 3_SLCK | WKUPx shall be in its active state for at least 3 SLOW_CLK periods |
| 2 | 32_SLCK | WKUPx shall be in its active state for at least 32 SLOW_CLK periods |
| 3 | 512_SLCK | WKUPx shall be in its active state for at least 512 SLOW_CLK periods |
| 4 | 4096_SLCK | WKUPx shall be in its active state for at least 4,096 SLOW_CLK periods |
| 5 | 32768_SLCK | WKUPx shall be in its active state for at least 32,768 SLOW_CLK periods |
Bit 7 – LPDBCCLR Low-power Debouncer Clear
| Value | Name | Description |
|---|---|---|
| 0 | NOT_ENABLE | A low-power debounce event does not create an immediate clear on the first half of GPBR registers. |
| 1 | ENABLE | A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. |
Bit 6 – LPDBCEN1 Low-power Debouncer Enable WKUP1
| Value | Name | Description |
|---|---|---|
| 0 | NOT_ENABLE | The WKUP1 input pin is not connected to the low-power debouncer. |
| 1 | ENABLE | The WKUP1 input pin is connected to the low-power debouncer and forces a system wakeup. |
Bit 5 – LPDBCEN0 Low-power Debouncer Enable WKUP0
| Value | Name | Description |
|---|---|---|
| 0 | NOT_ENABLE | The WKUP0 input pin is not connected to the low-power debouncer. |
| 1 | ENABLE | The WKUP0 input pin is connected to the low-power debouncer and forces a system wakeup. |
Bit 3 – RTCEN Real-Time Clock Wakeup Enable
| Value | Name | Description |
|---|---|---|
| 0 | NOT_ENABLE | The RTC alarm signal has no wakeup effect. |
| 1 | ENABLE | The RTC alarm signal forces the wakeup of the core power supply. |
Bit 2 – RTTEN Real-Time Timer Wakeup Enable
| Value | Name | Description |
|---|---|---|
| 0 | NOT_ENABLE | The RTT alarm signal has no wakeup effect. |
| 1 | ENABLE | The RTT alarm signal forces the wakeup of the core power supply. |
Bit 1 – SMEN Supply Monitor Wakeup Enable
| Value | Name | Description |
|---|---|---|
| 0 | NOT_ENABLE | The supply monitor detection has no wakeup effect. |
| 1 | ENABLE | The supply monitor detection forces the wakeup of the core power supply. |