24.5.1 SUPC Control Register
| Name: | SUPC_CR |
| Offset: | 0x00 |
| Reset: | - |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| XTALSEL | VROFF | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
Bits 31:24 – KEY[7:0] Password
| Value | Name | Description |
|---|---|---|
| 0xA5 | PASSWD | Writing any other value in this field aborts the write operation. |
Bit 3 – XTALSEL Crystal Oscillator Select
Note: This bit is located in the VDDIO domain.
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | CRYSTAL_SEL | If KEY is correct, XTALSEL switches the slow clock on the 32.768 kHz crystal oscillator output. |
Bit 2 – VROFF Voltage Regulator Off
Note: This bit is located in the VDDIO domain.
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | STOP_VREG | If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. |