24.5.6 SUPC Status Register

Note: Due to the asynchronism between the Slow Clock (SLOW_CLK) and the System Clock (MAIN_CLK), the status register flag reset is taken into account only two slow clock cycles after the read of the SUPC_SR.

Note: This register is located in the VDDIO domain.

Name:	SUPC_SR
Offset:	0x14
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
			WKUPIS13	WKUPIS12	WKUPIS11	WKUPIS10	WKUPIS9	WKUPIS8
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	WKUPIS7	WKUPIS6	WKUPIS5	WKUPIS4	WKUPIS3	WKUPIS2	WKUPIS1	WKUPIS0
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
		LPDBCS1	LPDBCS0
Access		R	R
Reset		0	0


Bit	7	6	5	4	3	2	1	0
	OSCSEL	SMOS	SMS	SMRSTS	BODRSTS	SMWS	WKUPS
Access	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 – WKUPISx Wakeup Input Status x (cleared on read)

Value	Name	Description
0	DIS	The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event.
1	EN	The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR.

Bit 14 – LPDBCS1 Low-power Debouncer Wakeup Status on WKUP1 (cleared on read)

Value	Name	Description
0	NO	No wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
1	PRESENT	At least one wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.

Bit 13 – LPDBCS0 Low-power Debouncer Wakeup Status on WKUP0 (cleared on read)

Value	Name	Description
0	NO	No wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
1	PRESENT	At least one wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.

Bit 7 – OSCSEL 32-kHz Oscillator Selection Status

Value	Name	Description
0	RC	The slow clock, SLOW_CLK, is generated by the slow RC oscillator.
1	CRYST	The slow clock, SLOW_CLK, is generated by the 32.768 kHz crystal oscillator.

Bit 6 – SMOS Supply Monitor Output Status

Value	Name	Description
0	HIGH	The supply monitor detected higher than its threshold at its last measurement.
1	LOW	The supply monitor detected lower than its threshold at its last measurement.

Bit 5 – SMS Supply Monitor Status (cleared on read)

Value	Name	Description
0	NO	No supply monitor detection since the last read of SUPC_SR.
1	PRESENT	At least one supply monitor detection since the last read of SUPC_SR.

Bit 4 – SMRSTS Supply Monitor Reset Status (cleared on read)

Value	Name	Description
0	NO	No supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1	PRESENT	At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.

Bit 3 – BODRSTS Brownout Detector Reset Status (cleared on read)

When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detection cell. The rising edge event occurs only when there is a voltage transition below the threshold.

Value	Name	Description
0	NO	No core brownout rising edge event has been detected since the last read of the SUPC_SR.
1	PRESENT	At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.

Bit 2 – SMWS Supply Monitor Detection Wakeup Status (cleared on read)

Value	Name	Description
0	NO	No wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR.
1	PRESENT	At least one wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR.

Bit 1 – WKUPS WKUP Wakeup Status (cleared on read)

Value	Name	Description
0	NO	No wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1	PRESENT	At least one wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.