14.7.2 Debug Architecture

Figure 14-4 shows the debug architecture used. The Cortex-M7 embeds the following six functional units for debug:

  • Serial Wire Debug Port (SW-DP) debug access
  • Flash Patch Breakpoint (FPB)
  • Data Watchpoint and Trace (DWT)
  • ITM (Instrumentation Trace Macrocell (ITM)
  • 6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight Trace Port Interface Unit (TPIU)
  • IEEE 1149.1 JTAG Boundary scan on all digital pins

The debug architecture information that follows is mainly dedicated to developers of SW-DP Emulators/Probes and debugging tool vendors for Cortex-M7-based microcontrollers. For additional information on SW-DP, refer to the "Cortex -M7 Technical Reference Manual".

Figure 14-4. Debug Architecture