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34.8.9 XDMAC Global Channel Disable Register Name: XDMAC_GD Offset: 0x20 Reset: – Property: Write-only
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 DI23 DI22 DI21 DI20 DI19 DI18 DI17 DI16 Access W W W W W W W W Reset – – – – – – – –
Bit 15 14 13 12 11 10 9 8 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 Access W W W W W W W W Reset – – – – – – – –
Bit 7 6 5 4 3 2 1 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Access W W W W W W W W Reset – – – – – – – –
XDMAC Channel x
Disable
Value Description
0
This bit has
no effect.
1
Disables
channel x.
On this page
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – DI XDMAC Channel x
Disable
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