34.8.21 XDMAC Channel n Interrupt Status Register

Name: XDMAC_CISn
Offset: 0x5C + n*0x40 [n=0..23]
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  ROISWBEISRBEISFISDISLISBIS 
Access RRRRRRR 
Reset 0000000 

Bit 6 – ROIS Request Overflow Error Interrupt Status Bit

ValueDescription
0 Overflow condition has not occurred.
1 Overflow condition has occurred at least once. (This information is only relevant for peripheral synchronized transfers.)

Bit 5 – WBEIS Write Bus Error Interrupt Status Bit

ValueDescription
0 Write bus error condition has not occurred.
1 At least one bus error has been detected in a write access since the last read of the Status register.

Bit 4 – RBEIS Read Bus Error Interrupt Status Bit

ValueDescription
0 Read bus error condition has not occurred.
1 At least one bus error has been detected in a read access since the last read of the Status register.

Bit 3 – FIS End of Flush Interrupt Status Bit

ValueDescription
0 End of flush condition has not occurred.
1 End of flush condition has occurred since the last read of the Status register.

Bit 2 – DIS End of Disable Interrupt Status Bit

ValueDescription
0 End of disable condition has not occurred.
1 End of disable condition has occurred since the last read of the Status register.

Bit 1 – LIS End of Linked List Interrupt Status Bit

ValueDescription
0 End of linked list condition has not occurred.
1 End of linked list condition has occurred since the last read of the Status register.

Bit 0 – BIS End of Block Interrupt Status Bit

ValueDescription
0 End of block interrupt has not occurred.
1 End of block interrupt has occurred since the last read of the Status register.