8.2.9 Peripheral Access Control Register 2
| Name: | PACCON2 |
| Offset: | 0x1EC4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| OPAMP3WR | OPAMP2WR | OPAMP1WR | MBISTCONWR | PMDWR | RPCONWR | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WDTCONWR | CM4RANGEWR | CM4CONWR | CM3RANGEWR | CM3CONWR | CM2RANGEWR | CM2CONWR | CM1RANGEWR | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OPAMP3LK | OPAMP2LK | OPAMP1LK | MBISTCONLK | PMDLK | RPCONLK | ||||
| Access | S/R | S/R | S/R | S/R | S/R | S/R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WDTCONLK | CM4RANGELK | CM4CONLK | CM3RANGELK | CM3CONLK | CM2RANGELK | CM2CONLK | CM1RANGELK | ||
| Access | S/R | S/R | S/R | S/R | S/R | S/R | S/R | S/R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – OPAMP3WR Op Amp 3 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 30 – OPAMP2WR Op Amp 2 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 29 – OPAMP1WR Op Amp 1 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 28 – MBISTCONWR MBIST Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 25 – PMDWR Peripheral Modules Disable Registers Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 24 – RPCONWR Peripheral Remapping Control Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 23 – WDTCONWR Watchdog Timer Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 22 – CM4RANGEWR Clock Monitor 4 Range (CM4WINPR - CM4LWARN) Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 21 – CM4CONWR Clock Monitor 4 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 20 – CM3RANGEWR Clock Monitor 3 Range (CM3WINPR - CM3LWARN) Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 19 – CM3CONWR Clock Monitor 3 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 18 – CM2RANGEWR Clock Monitor 2 Range (CM2WINPR - CM2LWARN) Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 17 – CM2CONWR Clock Monitor 2 Control Register Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 16 – CM1RANGEWR Clock Monitor 1 Range (CM1WINPR - CM1LWARN) Write Enable bit
| Value | Description |
|---|---|
| 1 | Register is writable. |
| 0 | Register is not writable. |
Bit 15 – OPAMP3LK Op Amp 3 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 14 – OPAMP2LK Op Amp 3 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 13 – OPAMP1LK Op Amp 1 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 12 – MBISTCONLK MBIST Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 9 – PMDLK Peripheral Modules Disable Registers Lock bit
| Value | Description |
|---|---|
| 1 | Registers are write locked. |
| 0 | Registers are not write locked. |
Bit 8 – RPCONLK Peripheral Remapping Configuration Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 7 – WDTCONLK Watchdog Timer Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 6 – CM4RANGELK Clock Monitor 4 Range Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 5 – CM4CONLK Clock Monitor 4 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 4 – CM3RANGELK Clock Monitor 3 Range Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 3 – CM3CONLK Clock Monitor 3 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 2 – CM2RANGELK Clock Monitor 2 Range (CM2WINPR - CM2LWARN) Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 1 – CM2CONLK Clock Monitor 2 Control Register Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |
Bit 0 – CM1RANGELK Clock Monitor 1 Range (CM1WINPR - CM1LWARN) Lock bit
| Value | Description |
|---|---|
| 1 | Register is write locked. |
| 0 | Register is not write locked. |