4.4.1 Arbitration
The BMX supports a decentralized fixed priority arbitration scheme. Each target has an independent arbitrator that will grant read and write requests to an initiator when that target is available. The default priority of an initiator is fixed and determined by the initiator’s index on the bus. The priorities are shown in Table 4-2.
| Priority | Initiator Index | Type |
|---|---|---|
| Highest | 0 | CPU X Data Bus (CPU XDS) |
| 1 | CPU Y Data Bus (CPU YDS) | |
| 2 | DMA | |
| 3 | CPU Instruction Bus (CPU IS) | |
| 4 | Crypto | |
| 5 | CAN1 | |
| 6 | NVM | |
| Lowest | 7 | In-circuit Debugger |