16.1 Device-Specific Information

Table 16-1. ADC Summary Table
Number of Cores	Max Number of Channels	Max Input Clock	Clock Source	Peripheral Bus Speed
3	12	320 MHz	CLKGEN6	Fast (1:1 CPU Clock)

The number of available positive and negative analog inputs is dependent on package size, as shown in the table below.

Table 16-2. ADC Input Availability
ADC Input	32-Pin	48-Pin	64-Pin	Comments
AD1ANN0	AV_SS			ADC 1 ground negative input 0 supporting differential mode
AD1ANN1		x	x	ADC 1 negative input 1 supporting differential mode
AD1ANN2	x	x	x	ADC 1 negative input 2 supporting differential mode
AD1ANN3	Reserved			Reserved
AD1AN0	x	x	x	ADC 1 positive input 0
AD1AN1	x	x	x	ADC 1 positive input 1
AD1AN2	x	x	x	ADC 1 positive input 2
AD1AN3		x	x	ADC 1 positive input 3
AD1AN4	x	x	x	ADC 1 positive input 4
AD1AN5	Reserved			Reserved
AD1AN6	Internal			ADC 1 0.8V Bandgap
AD1AN7	Internal			ADC 1 UREF input
AD1AN8	Internal			ADC 1 15/16AV_DD or 1/16AV_DD reference input
AD2ANN0	AV_SS			ADC 2 ground negative input 0 supporting differential mode
AD2ANN1	x	x	x	ADC 2 negative input 1 supporting differential mode
AD2ANN2	x	x	x	ADC 2 negative input 2 supporting differential mode
AD2ANN3	Reserved			Reserved
AD2AN0	x	x	x	ADC 2 positive input 0
AD2AN1	x	x	x	ADC 2 positive input 1
AD2AN2	x	x	x	ADC 2 positive input 2
AD2AN3	x	x	x	ADC 2 positive input 3
AD2AN4	x	x	x	ADC 2 positive input 4
AD2AN5	x	x	x	ADC 2 positive input 5
AD2AN6	Internal			ADC 2 0.8V Bandgap
AD2AN7	Internal			ADC 2 UREF input
AD2AN8	Internal			ADC 2 15/16AV_DD or 1/16AV_DD reference input
AD3ANN0	AV_SS			ADC 3 ground negative input 0 supporting differential mode
AD3ANN1	x	x	x	ADC 3 negative input 1 supporting differential mode
AD3ANN2	x	x	x	ADC 3 negative input 2 supporting differential mode
AD3ANN3	Reserved			Reserved
AD3AN0	x	x	x	ADC 3 positive input 0
AD3AN1	x		x	ADC 3 positive input 1
AD3AN2	x	x	x	ADC 3 positive input 2
AD3AN3		x	x	ADC 3 positive input 3
AD3AN4	x	x	x	ADC 3 positive input 4
AD3AN5	Reserved			Reserved
AD3AN6	Internal			ADC 3 0.8V Bandgap
AD3AN7	Internal			ADC 3 UREF input
AD3AN8	Internal			ADC 2 15/16AV_DD or 1/16AV_DD reference input
AD3AN9	Internal			ADC 3 V_DDCORE input

Table 16-3. TRGnSRC Trigger Source Selection Bits
Value	Description
`11000`	QEI1
`10111`	RDC
`10110`	SCCP4
`10101`	SCCP3
`10100`	SCCP2
`10011`	SCCP1
`10010`	PTG
`10001`	SCCP5 (MCCP)
`10000`	CLC4
`1111`	CLC3
`1110`	CLC2
`1101`	CLC1
`1100`	ITC
`1011`	PWMGEN 4
`1010`	PWMGEN 4
`1001`	PWMGEN 3
`1000`	PWMGEN 3
`111`	PWMGEN 2
`110`	PWMGEN 2
`101`	PWMGEN 1
`100`	PWMGEN 1
`11`	Conversion repeat timer trigger defined by RPTCNT[5:0] (ADnCON[23:18]) bits
`10`	Immediate re-trigger request
`01`	Software trigger initiated by using the ADnSWTRG register
`0`	Triggers are disabled