28.3.3 CCPx Control Register 3

Note:

ONESHOT (CCPxCON1[22]) must be set for the OSCNT[2:0] bits to be effective.
These bits are implemented in MCCP mode only.

Name:	CCPxCON3
Offset:	0x1B08, 0x1B38, 0x1B68, 0x1B98, 0x1BC8


Bit	31	30	29	28	27	26	25	24
	OETRIG	OSCNT[2:0]				OUTM[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	23	22	21	20	19	18	17	16
			POLACE	POLBDF	PSSACE[1:0]		PSSBDF[1:0]
Access			R/W	RW	R/W	R/W	RW	RW
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
			DT[5:0]
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0

Bit 31 – OETRIG Output Enable on Trigger Control bit

Value	Description
`1`	For Triggered mode (TRIGEN = `1`), the module does not drive enabled output pins until triggered.
`0`	Normal output pin operation

Bits 30:28 – OSCNT[2:0] One-Shot Count bits⁽¹⁾

Value	Description
`111`	Extends one-shot trigger event by 7 time base count cycles (8 time base periods total).
`110`	Extends one-shot trigger event by 6 time base count cycles (7 time base periods total).
`101`	Extends one-shot trigger event by 5 time base count cycles (6 time base periods total).
`100`	Extends one-shot trigger event by 4 time base count cycles (4 time base periods total).
`011`	Extends one-shot trigger event by 3 time base count cycles (4 time base periods total).
`010`	Extends one-shot trigger event by 2 time base count cycles (3 time base periods total).
`001`	Extends one-shot trigger event by 1 time base count cycle (2 time base periods total).
`000`	Does not extend one-shot trigger event.

Bits 26:24 – OUTM[2:0] Output Mode Control bits⁽²⁾

Value	Description
111-001	Reserved
000	Steerable Single Output mode

Bit 21 – POLACE CCP Output Pin, OCxA, Polarity Control bit

Value	Description
`1`	Output pin polarity is active-low.
`0`	Output pin polarity is active-high.

Bit 20 – POLBDF CCP Output Pins OCxB, OCxD and OCxF Polarity Control bit

Value	Description
1	Output pin polarity is active low.
0	Output pin polarity is active high.

Bits 19:18 – PSSACE[1:0] PWM Output Pin, OCxA, Shutdown State Control bits

Value	Description
`11`	Pins are driven active when a shutdown event occurs.
`10`	Pins are driven inactive when a shutdown event occurs.
`0x`	Pins are tri-stated when a shutdown event occurs.

Bits 17:16 – PSSBDF[1:0] PWM Output Pins OCxB, OCxD, and OCxF Shutdown State Control bits

Value	Description
11	Pins are driven active when a shutdown event occurs.
10	Pins are driven inactive when a shutdown event occurs.
0x	Pins are tri-stated when a shutdown event occurs.

Bits 5:0 – DT[5:0] Capture/Compare/PWM Deadtime Select bits⁽²⁾

Value	Description
111111	Insert 63 dead time delay periods between complementary output signals.
000010	Insert 2 dead time delay periods between complementary output signals
000001	Insert 1 dead time delay period between complementary output signals.
000000	Dead time logic disabled.

DS70005629B

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