3.4 Receiver

The signal is received from the wireless medium and sent to the FPGA through AD9371 using the JESD interface at the receiver. The signal is further processed in the FPGA to recover the transmitted message or data and the incoming data from the JESD is stored in the FIFO. The DC removal block reads the data from the FIFO and removes the DC offset, which is then amplified in the AGC. The Costas loop (closed loop) is used to remove the phase offset. A Cascaded Integrator-Comb (CIC) filter decimated the phase and frequency corrected signal. Symbol Timing Synchronisation is used to find the optimal sampling instance of the filtered signal.

The MPSK demodulation block demodulates the data and is decoded in the Viterbi decoder. SIPO collects the bit data and converts it into byte data. The received data contains the access code and packet length, which need to be matched at depacketization and the data is separated from the packet structure and stored in a FIFO. The data is read from the FIFO through the UART interface and displayed in the GUI at the receiver end.