3.8 Ports

The following table lists the ports of the demo design.

Table 3-1. Input and Output Ports
Port Name	Direction	Description
RefClock
REF_CLK_PAD_P_0 REF_CLK_PAD_N_0	Input	XCVR Reference clock 156.25 MHz
LANE0_TXD_N_0 LANE0_TXD_P_0	Output	XCVR serial data
JESD and Transceiver Peripheral Ports
REF_CLK_PAD_P REF_CLK_PAD_N	Input	XCVR Reference clock input
DAC_SYNC_P DAC_SYNC_N	Input	Sync signal from AD9371
PADP PADN	Input	SYSREF signal from AD9371 FMC card
LANE3_RXD_N LANE3_RXD_P LANE2_RXD_N LANE2_RXD_P LANE1_RXD_N LANE1_RXD_P LANE0_RXD_N LANE0_RXD_P	Input	Transceiver lanes connected to AD9371
ADC_SYNC_P ADC_SYNC_N	Output	Sync signal to AD9371
LED_OUT	Output	Connected to LEDs on EVAL kit
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P	Output	Transceiver lanes connected to AD9371
MSS Peripheral Ports
REF_CLK_0	Input	On Board 50 MHZ reference clock
TRSTB	Input	CoreJTAG pin
TCK	Input	CoreJTAG pin
TDI	Input	CoreJTAG pin
TMS	Input	CoreJTAG pin
SPI_SDI	Input	SPI Data input
TDO	Output	CoreJTAG pin
SPI_SCLK	Output	SPI Clock
SPI_SDO	Output	SPI Data out
SPI_SS0	Output	SPI chip select
SPI_SS1	Output	SPI chip select
GPIO_OUT	Output	GPIO[3] → reset JESD sub system GPIO[2] → UART MUX GPIO[4-9] → Connected to AD9371
UART Ports
RX	Input	UART receiver for both UARTapb and CoreUART
TX	Output	UART transmitter for both UARTapb and CoreUART

AN5014