3.3 Transmitter

The data to be transmitted is entered in the UART based Graphical User Interface (GUI) in the form of a text message or the text data is chosen from a text file. Each maximum SDR packet length is defined as 1024 Bytes. If the message is greater than 1024 Bytes, then the message is divided into chunks of 1024 Bytes data. The message is passed to FPGA through UART Interface and is stored in a FIFO. Once a complete packet is written into FIFO, the SDR packet is created by appending 64 Bytes access code and 2 Bytes of Packet length at the start of the packet. Final data transmitted from the packetization is 64 Bytes of access code + 2 Bytes of Packet Length + n Bytes of message (n is the size of the packet and is limited to 1024).

From Packetization, the message is further serialized from byte to bit in Parallel In Serial Out (PISO). Transformed bit data is further encoded using FEC Encoder with code rate of 1/2 to minimize the bit errors while transmitting in a noisy environment. The encoded data is modulated into Quadrature Phase Shift Keying (QPSK) constellation and then passed through the pulse shaping filter, which reduces the Inter Symbol Interference (ISI) and adjacent channel interference. Pulse shaped data is sent to AD9371 using JESD Interface. From AD9371, the data is transmitted through wireless medium to the receiver.