2.3.3.7 Using Double Data Rate (DDR)

In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very high-speed systems.

To implement a DDR, users need to:

Instantiate an input buffer (with the required I/O standard).
Instantiate the DDR_REG macro (see the following figure).
Connect the output from the input buffer to the input of the DDR macro.

The following figure shows DDR register.

Figure 2-6. DDR Register

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