2.3.3.4 Customizing the I/O

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A five-bit programmable input delay element is associated with each I/O. The value of this delay is set on a bank-wide basis (see the following table). It is optional for each input buffer within the bank (that is, the user can enable or disable the delay element for the I/O). When the input buffer drives a register within the I/O, the delay element is activated by default to ensure a zero hold-time. The default setting for this property can be set in Designer. When the input buffer does not drive a register, the delay element is deactivated to provide higher performance. Again, this can be overridden by changing the default setting for this property in Designer.

The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow or fast.

The drive strength value for LVTTL output buffers can be programmed as well. There are four different drive strength values (8 mA, 12 mA, 16 mA, or 24 mA) that can be specified in Designer.^⁵

The following table lists the values of bank-wide delay.

Table 2-19. Bank-Wide Delay Values
Bits Setting	Delay (ns)
0	0.54
1	0.65
2	0.71
3	0.83
4	0.9
5	1.01
6	1.08
7	1.19
8	1.27
9	1.39
10	1.45
11	1.56
12	1.64
13	1.75
14	1.81
15	1.93
16	2.01
17	2.13
18	2.19
19	2.3
20	2.38
21	2.49
22	2.55
23	2.67
24	2.75
25	2.87
26	2.93
27	3.04
28	3.12
29	3.23
30	3.29
31	3.41

Note: Delay values are approximate and will vary with process, temperature, and voltage.

These values are minimum drive strengths.