20.5.4 Machine Check Reset Flags B
A Power-on Reset (POR) will clear all flags.
| Name: | MCFLAGSB |
| Offset: | 0x03 |
| Reset: | 0xXX |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UPDI | CFD | ||||||||
| Access | R/W | R/W | |||||||
| Reset | x | x |
Bit 1 – UPDI Illegal Bus Activity Detected
This flag is cleared by writing a ‘1’ to it.
This bit is set if the internal consistency check detects that the UPDI bus controller is active when it should not be, such as when the device is locked.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Illegal Bus Activity Detected flag.
Bit 0 – CFD Clock Failure Detected
This flag is cleared by writing a ‘1’ to it.
This bit is set if a CFD monitor triggers a system Reset.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Clock Failure Detected flag.
