20.5.3 Machine Check Flags A


Bit	7	6	5	4	3	2	1	0
	VREG	CRC	WDT	BOOT	DCLS	EC	DFT	OCD
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	x	x	x	x	x	x	x	x

Bit 7 – VREG Voltage Regulator Monitor has Tripped

This flag is cleared by writing a ‘1’ to it.

This flag is set if the VREG monitor generates a system reset.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Voltage Regulator Monitor has Tripped flag.

Bit 6 – CRC CRC Scan Error

This flag is cleared by writing a ‘1’ to it.

This bit is set if the CRC Scan module detects a CRC error while scanning Flash during the boot sequence and generates a system Reset.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the CRC Scan Error flag.

Bit 5 – WDT WDT Clock Failure Monitor has Tripped

This flag is cleared by writing a ‘1’ to it.

This bit is set if the WDT clock failure monitor generates a system Reset.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the WDT Clock Failure Monitor has Tripped flag.

Bit 4 – BOOT Error detected during System Start-up

This flag is cleared by writing a ‘1’ to it.

This bit is set if detecting an error during system startup that generates a system Reset. This includes errors found during the CRC scan of the Boot ROM.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Error detected during System Start-up flag.

Bit 3 – DCLS Dual Core Lockstep Comparator Mismatch

This flag is cleared by writing a ‘1’ to it.

This bit is set if the DCLSC generates a system Reset.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Dual Core Lockstep Comparator Mismatch flag.

Bit 2 – EC Error Controller Internal Error

This flag is cleared by writing a ‘1’ to it.

This bit is set if the Error Controller generates a system Reset.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Error Controller Internal Error flag.

Bit 1 – DFT Design-For-Test Mechanisms Enabled

This flag is cleared by writing a ‘1’ to it.

This bit is set if the internal consistency check detects that the Design-For-Test feature has been erroneously enabled.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the Design-For-Test Mechanisms Enabled flag.

Bit 0 – OCD OCD System Enabled

This flag is cleared by writing a ‘1’ to it.

This bit is set if the internal consistency check detects that the OCD system has been erroneously enabled.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the OCD System Enabled flag.

Name:	MCFLAGSA
Offset:	0x02
Reset:	0xXX
Property:	-