9.3.2 CRC Scan of Flash

You can configure the CRCSCAN peripheral to perform a memory scan of the Boot Section in Flash before the device leaves the reset state. If this check fails, the CPU is prohibited from starting normal code execution. CRC scanning of Flash during start-up is enabled and controlled by the CRCBOOT bit in FUSE.SYSCFG0.

A successful CRC scan of Flash will have the following outcome:

• Normal code execution starts
• The DONE flag in the Interrupt Flags (CRCSCAN.INTFLAGS) register will be ‘1’
• The OK bit in the Status A (CRCSCAN.STATUSA) register will be ‘1’

A non-successful CRC scan will have the following outcome:

• The OK bit in CRCSCAN.STATUSA will be ‘0’
• If the device is locked:
  • MCHKRF in RSTCTRL.RSTFR is set and the CRC Scan Error (CRC) bit in RSTCTRL.MCFLAGSA is set
  • The device is reset, restarting execution at the start of the Boot ROM Code
• If the device is not locked:
  • The device is NOT reset
  • The CPU executes an eternal loop in the Boot ROM Code, waiting for a UPDI command or a reset
  • You can observe this condition by using the UPDI interface

A non-correctable 2-bit (ECC2) error detected in Flash during a CRC Scan will cause a CRCSCAN failure. A CRC scan of unprogrammed Flash will always result in ECC2 errors, causing the CRC Scan to fail. Therefore, the entire Boot Section of the Flash must be programmed with ECC-valid content if CRCBOOT in FUSE.SYSCFG0 is set.