23.3.2.3 Event Generators

Each event channel has several possible event generators, but only one can be selected at a time. The event generator for a channel is selected by writing to the respective Channel n Generator Selection (EVSYS.CHANNELn) register. By default, the channels are not connected to any event generator. For details on event generation, refer to the documentation of the corresponding peripheral.

A generated event is either synchronous or asynchronous to the device peripheral clock (CLK_PER). Asynchronous events can be generated outside the normal edges of the peripheral clock, making the system respond faster than the selected clock frequency would suggest. Asynchronous events can also be generated while the device is in a sleep mode when the peripheral clock is not running.

Any generated event is classified as either a pulse event or a level event. In both cases, the event can be either synchronous or asynchronous, with properties according to the table below.

Table 23-1. Properties of Generated Events
Event Type	Sync/Async	Description
Pulse	Sync	An event generated from CLK_PER that lasts one clock cycle
Pulse	Async	An event generated from a clock other than CLK_PER lasting one clock cycle
Level	Sync	An event generated from CLK_PER that lasts multiple clock cycles
Level	Async	An event generated without a clock (for example, a pin or a comparator), or an event generated from a clock other than CLK_PER that lasts multiple clock cycles

The properties of both the generated event and the intended event user must be considered in order to ensure reliable and predictable operation.

The table below shows the available event generators for this device family.

Table 23-2. Event Generators
Generator Name		Description	Event Type	Generating Clock Domain	Length of Event
Peripheral	Event	Description	Event Type	Generating Clock Domain	Length of Event
UPDI	SYNCH	SYNCH character	Level	CLK_PDI	SYNCH character on PDI RX input synchronized to CLK_PDI
WDT	TICK	WDT LSB Tick	Level	CLK_WDT
SWDT	ERROR	SWDT Error	Pulse	CLK_PER
MVIO	VDDIO2OK	VDDIO2 is OK	Level	CLK_PER
RTC	OVF	Overflow	Pulse	CLK_RTC	One CLK_RTC period
	CMP	Compare Match	Pulse		One CLK_RTC period
	EVGENn	Selectable prescaled RTC event	Level		Prescaled CLK_RTC period
CCL	LUTn	LUT output level	Level	Asynchronous	Depends on the CCL configuration
ACn	OUT	Comparator output level	Level	Asynchronous	Given by the AC output level
ADCn	RESRDY	Result ready	Pulse	CLK_PER	One CLK_PER period
	SAMPRDY	Sample ready
	WCMP	Window compare
ZCDn	OUT	ZCD output level	Level	Asynchronous	Given by the ZCD output level
PORTx	EVGENn	Pin level	Level	Asynchronous	Given by the pin level
USARTn	XCK	USART baud clock	Level	CLK_PER	Minimum two CLK_PER periods
SPIn	SCK	SPI host clock	Level	CLK_PER	Minimum two CLK_PER periods
TCAn	OVF_LUNF	Overflow/Low byte timer underflow	Pulse	CLK_PER	One CLK_PER period
	HUNF	High byte timer underflow
	CMP0_LCMP0	Compare channel 0 match/Low byte timer compare channel 0 match
	CMP1_LCMP1	Compare channel 1 match/Low byte timer compare channel 1 match
	CMP2_LCMP2	Compare channel 2 match/Low byte timer compare channel 2 match
TCBn	CAPT	CAPT flag set	Pulse	CLK_PER	One CLK_PER period
TCBn	OVF	Overflow	Pulse	CLK_PER	One CLK_PER period
TCDn	CMPBCLR	Counter matches CMPBCLR	Pulse	CLK_TCD	One CLK_TCD period
	CMPASET	Counter matches CMPASET
	CMPBSET	Counter matches CMPBSET
	PROGEV	Programmable event output