13.2 Interrupt Vector Mapping

Each of the interrupt vectors is connected to one peripheral instance, as shown in the table below. A peripheral can have one or more interrupt sources. For more details on the available interrupt sources, see the Interrupt section in the Functional Description of the respective peripheral.

An interrupt flag is set in the peripheral’s Interrupt Flags (peripheral.INTFLAGS) register when the interrupt condition occurs, even if the interrupt is not enabled.

An interrupt is enabled or disabled by writing to the corresponding interrupt enable bit in the peripheral’s Interrupt Control (peripheral.INTCTRL) register.

An interrupt request is generated when the corresponding interrupt is enabled, and the interrupt flag is set. Interrupts must be enabled globally for an interrupt request to be generated. The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for details on how to clear interrupt flags.

Table 13-3. Interrupt Vector Mapping

Vector Number	Program Address (word)	Interrupt Vector (name)	Interrupt Source (name)	Description	20-pin	28-pin	32-pin	48-pin
0	0x00	RESET	-	Device Reset interrupt	X	X	X	X
1	0x02	NMI	NMINONCRITICAL	Non-Maskable Non-Critical interrupt from ERRCTRL	X	X	X	X
			ERROR	Non-Maskable Error interrupt from CRCSCAN	X	X	X	X
			BUSERR	Non-Maskable Bus Error interrupt from CPU	X	X	X	X
			OPC	Non-Maskable Illegal Opcode interrupt from CPU	X	X	X	X
			PARITYD	Non-Maskable Parity Data Error interrupt from CPU	X	X	X	X
			PARITYI	Non-Maskable Parity Instruction Error from CPU	X	X	X	X
			SPLIM	Non-Maskable Stack Pointer Limit interrupt from CPU	X	X	X	X
2	0x04	BOD_VLM	VLM	Voltage Level Monitoring interrupt from BOD	X	X	X	X
3	0x06	ERRCTRL_INT	NONCRITICAL	Non-Critical interrupt from ERRCTRL	X	X	X	X
4	0x08	CLKCTRL_INT	CFD0	Clock Failure Detect 0 interrupt from CLKCTRL	X	X	X	X
			CFD1	Clock Failure Detect 1 interrupt from CLKCTRL	X	X	X	X
			CFMD0	Clock Frequency Measurement Done 0 interrupt from CLKCTRL	X	X	X	X
			CFMD1	Clock Frequency Measurement Done 1 interrupt from CLKCTRL	X	X	X	X
			CFM0	Clock Frequency Measurement Error 0 interrupt from CLKCTRL	X	X	X	X
			CFM0	Clock Frequency Measurement Error 1 interrupt from CLKCTRL	X	X	X	X
5	0x0A	SLPCTRL_INT	SERR	Sleep Error interrupt from SLPCTRL	X	X	X	X
			VDENTER	VMON Entered Diagnostic Mode interrupt from SLPCTRL	X	X	X	X
			VDEXIT	VMON Exited Diagnostic Mode interrupt from SLPCTRL	X	X	X	X
			VDIS	VMON Disabled interrupt from SLPCTRL	X	X	X	X
			VERR	VMON Error interrupt from SLPCTRL	X	X	X	X
			VOV	VMON Overvoltage interrupt from SLPCTRL	X	X	X	X
			VSLP	VMON Sleep interrupt from SLPCTRL	X	X	X	X
			VUV	VMON Undervoltage interrupt from SLPCTRL	X	X	X	X
6	0x0C	SWDT_INT	BADC	Bad Clear Command interrupt from SWDT	X	X	X	X
			BADPC	Bad Pre-Clear Command interrupt from SWDT	X	X	X	X
			EXP	Expired Counter interrupt from SWDT	X	X	X	X
			UC	Unexpected Command interrupt from SWDT	X	X	X	X
7	0x0E	NVMCTRL_ERROR	COMP	Comparator Mismatch interrupt from NVMCTRL	X	X	X	X
			EECC1	EEPROM ECC 1-bit Error interrupt from NVMCTRL	X	X	X	X
			EECC2	Flash ECC Multibit Error interrupt from NVMCTRL	X	X	X	X
			FECC1	Flash ECC 1-bit Error interrupt from NVMCTRL	X	X	X	X
			FECC2	Flash ECC Multibit Error interrupt from NVMCTRL	X	X	X	X
			PARITYA	Parity Address Error interrupt from NVMCTRL	X	X	X	X
			PARITYC	Parity Control Error interrupt from NVMCTRL	X	X	X	X
			PARITYD	Parity Data Error interrupt from NVMCTRL	X	X	X	X
8	0x10	RAMCTRL_INT	COMP	Comparator Mismatch interrupt from RAMCTRL	X	X	X	X
			ECC1	EEPROM ECC 1-bit Error interrupt from RAMCTRL	X	X	X	X
			ECC2	EEPROM ECC Multibit Error interrupt from RAMCTRL	X	X	X	X
			PARITYC	Parity Control Error interrupt from RAMCTRL	X	X	X	X
			PARITYA	Parity Address Error interrupt from RAMCTRL	X	X	X	X
			PARITYD	Parity Data Error interrupt from RAMCTRL	X	X	X	X
9	0x12	CRCSCAN_INT	DONE	Scan Period Done interrupt from CRCSCAN	X	X	X	X
9	0x12	CRCSCAN_INT	PERIOD	Period Done interrupt from CRCSCAN	X	X	X	X
10	0x14	MVIO_MVIO	VDDIO2	VDDIO2 interrupt from MVIO	X	X	X	X
11	0x16	RTC_CNT	CMP	Compare interrupt from RTC	X	X	X	X
11	0x16	RTC_CNT	OVF	Overflow interrupt from RTC	X	X	X	X
12	0x18	RTC_PIT	PIT	Periodic Interrupt Timer interrupt from RTC	X	X	X	X
13	0x1A	CCL_CCL	LUTn	LUTn interrupt from CCL	X	X	X	X
14	0x1C	PORTA_PORT	PAn	Pin n interrupt from PORTA	X	X	X	X
15	0x1E	TCA0_OVF	OVF	Overflow interrupt from TCA0 in Normal mode	X	X	X	X
15	0x1E	TCA0_OVF	LUNF	Low Byte Underflow interrupt from TCA0 in Split mode	X	X	X	X
16	0x20	TCA0_HUNF	HUNF	High Byte Overflow interrupt from TCA0 in Split mode	X	X	X	X
17	0x22	TCA0_CMP0	CMP0	Compare 0 interrupt from TCA0 in Normal mode	X	X	X	X
17	0x22	TCA0_CMP0	LCMP0	Low Compare 0 interrupt from TCA0 Split mode	X	X	X	X
18	0x24	TCA0_CMP1	CMP1	Compare 1 interrupt from TCA0 in Normal mode	X	X	X	X
18	0x24	TCA0_CMP1	LCMP1	Low Compare 1 interrupt from TCA0 Split mode	X	X	X	X
19	0x26	TCA0_CMP2	CMP2	Compare 2 interrupt from TCA0 in Normal mode	X	X	X	X
19	0x26	TCA0_CMP2	LCMP2	Low Compare 2 interrupt from TCA0 Split mode	X	X	X	X
20	0x28	TCB0_INT	CAPT	Capture interrupt from TCB0	X	X	X	X
20	0x28	TCB0_INT	OVF	Overflow interrupt from TCB0	X	X	X	X
21	0x2A	TCB1_INT	CAPT	Capture interrupt from TCB1	X	X	X	X
21	0x2A	TCB1_INT	OVF	Overflow interrupt from TCB1	X	X	X	X
22	0x2C	TCD0_OVF	OVF	Overflow interrupt from TCD0	X	X	X	X
23	0x2E	TCD0_TRIG	TRIGA	Trigger A interrupt from TCD0	X	X	X	X
23	0x2E	TCD0_TRIG	TRIGB	Trigger B interrupt from TCD0	X	X	X	X
24	0x30	TWI0_TWIS	DIF	Client Data Transmit or Receive Complete interrupt from TWI0 in Client mode	X	X	X	X
24	0x30	TWI0_TWIS	APIF	Client Address or Stop interrupt from TWI0 in Client mode	X	X	X	X
25	0x32	TWI0_TWIM	RIF	Host Read Complete interrupt from TWI0 in Host mode	X	X	X	X
25	0x32	TWI0_TWIM	WIF	Host Write Complete interrupt from TWI0 in Host mode	X	X	X	X
26	0x34	SPI0_INT	RXCIF	Receive Complete interrupt from SPI0 in Buffered mode	X	X	X	X
			TXCIF	Transmit Complete interrupt from SPI0 in Buffered mode	X	X	X	X
			DREIF	Data Register Empty interrupt from SPI0 in Buffered mode	X	X	X	X
			SSIF	Slave Select interrupt from SPI0 in Buffered mode	X	X	X	X
			IF	Transmit Complete interrupt from SPI0 in Normal mode	X	X	X	X
			WRCOL	Write Collision interrupt from SPI0 in Normal mode	X	X	X	X
27	0x36	SPI1_INT	RXC	Receive Complete interrupt from SPI1 in Buffered mode	X	X	X	X
			TXC	Transfer Complete interrupt from SPI1 in Buffered mode	X	X	X	X
			DRE	Data Register Empty interrupt from SPI1 in Buffered mode	X	X	X	X
			SS	Client Select interrupt from SPI1 in Buffered mode	X	X	X	X
			TXC	Transfer Complete interrupt from SPI1 in Normal mode	X	X	X	X
			WRCOL	Write Collision interrupt from SPI1 in Normal mode	X	X	X	X
28	0x38	USART0_RXC	RXCIF	Receive Complete interrupt from USART0	X	X	X	X
			RXSIF	Receive Start-of-Frame interrupt from USART0	X	X	X	X
			ISFIF	Auto-Baud Error interrupt from USART0	X	X	X	X
29	0x3A	USART0_DRE	DREIF	Data Register Empty interrupt from USART0	X	X	X	X
30	0x3C	USART0_TXC	TXCIF	Transmit Complete interrupt from USART0	X	X	X	X
31	0x3E	PORTD_INT	PDn	Pin n interrupt from PORTD	X	X	X	X
32	0x40	AC0_AC	CMP	Compare interrupt from AC0	X	X	X	X
33	0x42	AC1_AC	CMP	Compare interrupt from AC1	X	X	X	X
34	0x44	AC2_AC	CMP	Compare interrupt from AC2	X	X	X	X
35	0x46	ADC0_ERROR	TRIGOVR	Trigger Overrun interrupt from ADC0	X	X	X	X
			SAMPOVR	Sample Overwrite interrupt from ADC0	X	X	X	X
			RESOVR	Result Overwrite interrupt from ADC0	X	X	X	X
36	0x48	ADC0_RESRDY	RESRDY	Result Ready interrupt from ADC0	X	X	X	X
36	0x48	ADC0_RESRDY	WCMP	Window Compare interrupt from ADC0	X	X	X	X
37	0x4A	ADC0_SAMPRDY	SAMPRDY	Sample Ready interrupt from ADC0	X	X	X	X
37	0x4A	ADC0_SAMPRDY	WCMP	Window Compare interrupt from ADC0	X	X	X	X
38	0x4C	ADC1_ERROR	TRIGOVR	Trigger Overrun interrupt from ADC1	X	X	X	X
			SAMPOVR	Sample Overwrite interrupt from ADC1	X	X	X	X
			RESOVR	Result Overwrite interrupt from ADC1	X	X	X	X
39	0x4E	ADC1_RESRDY	RESRDY	Result Ready interrupt from ADC1	X	X	X	X
39	0x4E	ADC1_RESRDY	WCMP	Window Compare interrupt from ADC1	X	X	X	X
40	0x50	ADC1_SAMPRDY	SAMPRDY	Sample Ready interrupt from ADC1	X	X	X	X
40	0x50	ADC1_SAMPRDY	WCMP	Window Compare interrupt from ADC1	X	X	X	X
41	0x52	ZCD3_ZCD	CROSSIF	Cross interrupt from ZCD3	X	X	X	X
42	0x54	PORTC_PORT	PCn	Pin n interrupt from PORTC	X	X	X	X
43	0x56	USART1_RXC	RXCIF	Receive Complete interrupt from USART1	X	X	X	X
			RXSIF	Receive Start-of-Frame interrupt from USART1	X	X	X	X
			ISFIF	Auto-Baud Error intterupt from USART1	X	X	X	X
44	0x58	USART1_DRE	DREIF	Data Register Empty interrupt from USART1	X	X	X	X
45	0x5A	USART1_TXC	TXCIF	Transmit Complete interrupt from USART1	X	X	X	X
46	0x5C	PORTF_PORT	PFn	Pin n interrupt from PORTF	X	X	X	X
47	0x5E	NVMCTRL_READY	EEREADY	EEPROM Ready interrupt from NVMCTRL	X	X	X	X
48	0x60	TCB2_INT	CAPT	Capture interrupt from TCB2	X	X	X	X
48	0x60	TCB2_INT	OVF	Overflow interrupt from TCB2	X	X	X	X
49	0x62	TCB3_INT	CAPT	Capture interrupt from TCB3	X	X	X	X
49	0x62	TCB3_INT	OVF	Overflow interrupt from TCB3	X	X	X	X
50	0x64	ZCD0_ZCD	CROSSIF	Cross interrupt from ZCD0	-	X	X	X
51	0x66	USART2_RXC	RXCIF	Receive Complete interrupt from USART2	-	X	X	X
			RXSIF	Receive Start-of-Frame interrupt from USART2	-	X	X	X
			ISFIF	Auto-Baud Error interrupt from USART2	-	X	X	X
52	0x68	USART2_DRE	DREIF	Data Register Empty interrupt from USART2	-	X	X	X
53	0x6A	USART2_TXC	TXCIF	Transmit Complete interrupt from USART2	-	X	X	X
54	0x6C	TWI1_TWIS	DIF	Client Data Transmit or Receive Complete interrupt from TWI1 in Client mode	-	X	X	X
54	0x6C	TWI1_TWIS	APIF	Client Address or Stop interrupt from TWI1 in Client mode	-	X	X	X
55	0x6E	TWI1_TWIM	RIF	Host Read Complete interrupt from TWI1 in Host mode	-	X	X	X
55	0x6E	TWI1_TWIM	WIF	Host Write Complete interrupt from TWI1 in Host mode	-	X	X	X
56	0x70	PORTB_PORT	PBn	Pin n interrupt from PORTB	-	-	-	X
57	0x72	PORTE_PORT	PEn	Pin n interrupt from PORTE	-	-	-	X